Systems and methods for digital signal synthesis with variable sample rate DAC
Systems and methods for digital signal synthesis with variable sample rate digital-to-analog converters (DACs) in accordance with various embodiments of the invention are described. One embodiment includes a digital frequency generator that includes a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; a frequency control word (FCW); where the DAC is sampled by the variable frequency sample clock; where the DDFS is clocked by the variable frequency sample clock; where the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; where the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, where the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock.
1. A digital frequency generator comprising:
a direct digital frequency synthesizer (DDFS);
a digital-to-analog converter (DAC);
a frequency/phase estimation circuit;
a stable reference clock (REF CLK);
a variable frequency sample clock; and
a frequency control word (FCW);
wherein the DAC is sampled by the variable frequency sample clock;
wherein the DDFS is clocked by the variable frequency sample clock;
wherein the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS;
wherein the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, wherein the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock; and
wherein the DAC converts the digital sine codeword to an analog waveform.
2. The digital frequency generator of claim 1 , wherein the variable frequency sample clock is at least one variable frequency sample clock selected from the group consisting of a frequency ramp generator, a pseudo random (PN) modulated frequency source, and a frequency modulation source.
3. The digital frequency generator of claim 1 , wherein the frequency/phase estimation circuit estimates a frequency error by comparing edges of the REF CLK and the variable frequency sample clock, wherein the frequency error is filtered with a loop filter to generate the FCW for the DDFS.
4. The digital frequency generator of claim 1 , wherein the FCW is a ratio of a desired frequency (fc) and the variable frequency sample clock (fs j ) wherein j denotes an index of the sample frequency.
5. A broadband modulator comprising:
a stable symbol clock (CLK);
a variable frequency sample clock;
an OFDM modulator circuit that operates at the stable symbol CLK to generate OFDM symbols;
a frequency/phase estimation circuit that receives as inputs the stable symbol CLK and the variable frequency sample clock and estimates a frequency error and a phase error;
a variable interpolator/decimator (VID) circuit that uses the frequency error and the phase error to generate a codeword; and
a digital-to-analog converter (DAC) that receives the codeword from the VID and generates an analog output.
6. The broadband modulator of claim 5 , wherein the analog output is filtered by a filter to provide a filtered analog output.
7. The broadband modulator of claim 5 , wherein the VID circuit converts a modulated signal from the stable symbol CLK domain to the variable frequency sample clock domain, wherein the VID circuit generates a corrected codeword that is provided to the DAC.