IP Library › Granted Patent US 6,940,434
Granted Patent B2
US 6,940,434 · App. 10/861,377 · Granted Sep 6, 2005

Methods and systems for digital dither

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 6,940,434
App. No.
10/861,377
Granted
Sep 6, 2005
Kind
B2
Abstract

Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma data converters. In an embodiment, an analog signal from a first path of a delta-sigma modulator is quantized to an m-bit digital signal and an n-bit dithered digital feedback signal is generated from at least a portion of the m-bit digital signal. The n-bit dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator. In an embodiment, the n-bit dithered digital feedback signal is generated by selecting one of a plurality of sets of n-bits from the m-bit digital signal depending upon a state of a dither control signal. The dither control signal can alternate between a plurality of states or pseudo-randomly switch between a plurality of states. In an embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between bits 0 through m-2 and bits 1 through m-1 of the m-bit digital signal. In an alternative embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between even and odd bits of the m-bit digital signal.

Claims (24)

1. A method of applying digital dither, comprising the steps of:

(a) quantizing an analog signal to an m-bit digital signal;

(b) generating an n-bit dithered digital feedback signal from at least a portion of the m-bit digital signal;

(c) converting the n-bit dithered digital feedback signal to an analog feedback signal;

(d) feeding back the analog feedback signal to a second path of the delta-sigma modulator; and

(e) performing one or more feedback processes on at least one of the n-bit dithered digital feedback signal and the analog feedback signal.

2. The method of claim 1 , wherein the one or more feedback processes comprises mismatch shaping.

3. The method of claim 1 , wherein the one or more feedback processes comprises filtering.

4. The method of claim 1 , wherein the one or more feedback processes comprises integration.

5. The method of claim 1 , wherein the one or more feedback processes comprises selecting one or more feedback loops.

6. The method of claim 5 , wherein the one or more feedback processes further comprises selecting one or more inputs to the one or more feedback loops.

7. The method of claim 5 , wherein the one or more feedback processes further comprises selecting one or more outputs from said one or more feedback loops.

8. A delta-sigma modulator apparatus, comprising:

(a) means for quantizing an analog signal to an m-bit digital signal;

(b) means for generating an n-bit dithered digital feedback signal from at least a portion of the m-bit digital signal;

(c) means for converting the n-bit dithered digital feedback signal to an analog feedback signal;

(d) means for feeding back the analog feedback signal to a second path of the delta-sigma modulator; and

(e) means for performing one or more feedback processes on at least one of the n-bit dithered digital feedback signal and the analog feedback signal.

9. The apparatus of claim 8 , wherein the one or more feedback processes comprises mismatch shaping.

10. The apparatus of claim 8 , wherein the one or more feedback processes comprises filtering.

11. The apparatus of claim 8 , wherein the one or more feedback processes comprises integration.

12. The apparatus of claim 8 , wherein the one or more feedback processes comprises selecting one or more feedback loops.

13. The apparatus of claim 12 , wherein the one or more feedback processes further comprises selecting one or more inputs to the one or more feedback loops.

14. The apparatus of claim 12 , wherein the one or more feedback processes further comprises selecting one or more outputs from the one or more feedback loops.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
Continuity (5)
Continuation 1037222900 · Feb 25, 2003
Continuation 0994981600 · Sep 12, 2001
Provisional Application 6023217300 · Sep 11, 2000
Provisional Application 6023217600 · Sep 11, 2000
Related Publication 20040233084A1 · Nov 25, 2004