Delta-sigma modulator
A system and method to achieve low power and/or low supply operation of a delta-sigma modulator by taking advantage of the inherent virtual ground of the delta-sigma loop to make the input to a low power integrator small and largely independent of the input signal. This results in improved linearity of the integrator and relaxed constraints on the supply for the first stage integrator. The architecture also enables direct access to the quantization error of the feedback loop and thus can be used to either/or: 1. Calibrate the modulator, 2. Achieve reduced quantization noise, 3. Stabilize the loop by compensating for excess loop delay. Low voltage common-mode-feedback is also achieved using the techniques described.
1. A delta-sigma modulator configured to digitize an input analog signal, the delta-sigma modulator comprising:
a two port network device for receiving the input analog signal and outputting a first output analog signal;
a feedback DAC for receiving a digital input signal and outputting a second output analog signal, wherein the first output analog signal and the second output analog signal combine to form an integrator input voltage;
a first stage integrator generating a scaled integral voltage of the integrator input voltage, the first stage integrator including a substantially non-linear integrator that includes a Gm cell loaded by a capacitor; and
a virtual ground node formed by connecting the two port network device, the feedback DAC, and the first stage integrator, the virtual ground node configured to reduce swing and improve linearity.
2. The delta-sigma modulator of claim 1 , wherein the two port network device comprises an impedance.
3. The delta-sigma modulator of claim 2 , wherein the impedance is a resistor.
4. The delta-sigma modulator of claim 2 , wherein the impedance is a capacitor.
5. The delta-sigma modulator of claim 1 , wherein the two port network device comprises a transimpedance.
6. The delta-sigma modulator of claim 5 , wherein the transimpedance is a Gm cell.
7. The delta-sigma modulator of claim 1 , wherein the feedback DAC includes a voltage-in, voltage-out DAC and a second two port network device.
8. The delta-sigma modulator of claim 7 , wherein the output of the feedback DAC is a current.
9. The delta-sigma modulator of claim 7 , wherein the output of the feedback DAC is electrical charge.
10. The delta-sigma modulator of claim 7 , wherein the output of the feedback DAC is a voltage.
11. The delta-sigma modulator of claim 1 , further comprising an ADC connected to the virtual ground node, the ADC configured to digitize a quantization error.
12. The delta-sigma modulator of claim 11 , wherein the ADC is a delta-sigma modulator.
13. The delta-sigma modulator of claim 11 , further comprising a DSP connected to the ADC, the DSP configured to receive a signal from the ADC, the DSP configured to reduce the quantization error.
14. The delta-sigma modulator of claim 13 , wherein the DSP is configured to modify a NTF.
15. The delta-sigma modulator of claim 13 , further comprising a signal generator for injecting a test calibration signal into the delta-sigma modulator.
16. The delta-sigma modulator of claim 15 , wherein the DSP is configured to detect a non-ideality using the test calibration signal and to compensate for the non-ideality.
17. A delta-sigma modulator configured to digitize an input analog signal, the delta-sigma modulator comprising:
a two port network device for receiving the input analog signal and outputting a first output analog signal;
a feedback DAC for receiving a digital input signal and outputting a second output analog signal, wherein the first output analog signal and the second output analog signal combine to form an integrator input voltage;
a first stage integrator generating a scaled integral voltage of the integrator input voltage;
a virtual ground node formed by connecting the two port network device, the feedback DAC, and the first stage integrator, the virtual ground node configured to reduce swing and improve linearity;
an ADC connected to the virtual ground node, the ADC being configured to digitize a quantization error; and
a DSP connected to the ADC, the DSP configured to receive a signal from the ADC, the DSP being configured to reduce the quantization error, the DSP further being configured to modify a NTF.
18. The delta-sigma modulator of claim 17 , wherein the two port network device comprises an impedance.
19. The delta-sigma modulator of claim 18 , wherein the impedance is a resistor.
20. The delta-sigma modulator of claim 18 , wherein the impedance is a capacitor.
21. The delta-sigma modulator of claim 17 , wherein the two port network device comprises a transimpedance.
22. The delta-sigma modulator of claim 21 , wherein the transimpedance is a Gm cell.
23. The delta-sigma modulator of claim 17 , wherein the feedback DAC includes a voltage-in, voltage-out DAC and a second two port network device.
24. The delta-sigma modulator of claim 23 , wherein the output of the feedback DAC is a current.
25. The delta-sigma modulator of claim 23 , wherein the output of the feedback DAC is electrical charge.
26. The delta-sigma modulator of claim 23 , wherein the output of the feedback DAC is a voltage.
27. The delta-sigma modulator of claim 17 , wherein the ADC is a delta-sigma modulator.
28. The delta-sigma modulator of claim 17 , further comprising a signal generator for injecting a test calibration signal into the delta-sigma modulator.
29. The delta-sigma modulator of claim 28 , wherein the DSP is configured to detect a non-ideality using the test calibration signal and to compensate for the non-ideality.
30. A delta-sigma modulator configured to digitize an input analog signal, the delta-sigma modulator comprising:
a two port network device for receiving the input analog signal and outputting a first output analog signal;
a feedback DAC for receiving a digital input signal and outputting a second output analog signal, wherein the first output analog signal and the second output analog signal combine to form an integrator input voltage;
a first stage integrator generating a scaled integral voltage of the integrator input voltage;
a virtual ground node formed by connecting the two port network device, the feedback DAC, and the first stage integrator, the virtual ground node configured to reduce swing and improve linearity;
an ADC connected to the virtual ground node, the ADC being configured to digitize a quantization error;
a DSP connected to the ADC, the DSP configured to receive a signal from the ADC, the DSP being configured to reduce the quantization error; and
a signal generator for injecting a test calibration signal into the delta-sigma modulator.
31. The delta-sigma modulator of claim 30 , wherein the two port network device comprises an impedance.
32. The delta-sigma modulator of claim 31 , wherein the impedance is a resistor.
33. The delta-sigma modulator of claim 31 , wherein the impedance is a capacitor.
34. The delta-sigma modulator of claim 30 , wherein the two port network device comprises a transimpedance.
35. The delta-sigma modulator of claim 34 , wherein the transimpedance is a Gm cell.
36. The delta-sigma modulator of claim 30 , wherein the feedback DAC includes a voltage-in, voltage-out DAC and a second two port network device.
37. The delta-sigma modulator of claim 36 , wherein the output of the feedback DAC is a current.
38. The delta-sigma modulator of claim 36 , wherein the output of the feedback DAC is electrical charge.
39. The delta-sigma modulator of claim 36 , wherein the output of the feedback DAC is a voltage.
40. The delta-sigma modulator of claim 30 , wherein the ADC is a delta-sigma modulator.
41. The delta-sigma modulator of claim 30 , wherein the DSP is configured to detect a non-ideality using the test calibration signal and to compensate for the non-ideality.
42. A delta-sigma modulator configured to digitize an input analog signal, the delta-sigma modulator comprising:
a two port network device for receiving the input analog signal and outputting a first output analog signal, the two port network device including an impedance that includes a capacitor;
a feedback DAC for receiving a digital input signal and outputting a second output analog signal, wherein the first output analog signal and the second output analog signal combine to form an integrator input voltage;
a first stage integrator generating a scaled integral voltage of the integrator input voltage; and
a virtual ground node formed by connecting the two port network device, the feedback DAC, and the first stage integrator, the virtual ground node configured to reduce swing and improve linearity.