Methods and systems for high speed quantizers
Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.
1. A method for performing feedback processing in analog delta-sigma modulators, comprising the steps of:
(a) receiving a continuous-time analog signal from a first path of an analog delta-sigma modulator;
(b) sampling the received continuous-time analog signal at a first throughput rate, thereby generating a first discrete-time analog signal having the first throughput rate;
(c) converting the first discrete-time analog signal to a first digital signal having the first throughput rate;
(d) digitally processing the first digital signal in a pipeline at a second throughput rate that is higher than the first throughput rate, whereby samples of the first digital signal sequentially pass through a plurality of stages of the pipeline at the second throughput rate;
(e) generating a continuous-time analog feedback signal representative of at least a portion of the digitally processed first digital signal, whereby the continuous-time analog feedback signal is delayed in time relative to the received continuous-time analog signal;
(f) providing the continuous-time analog feedback signal to a second path of the delta-sigma modulator; and
(g) generating a second signal representative of the received continuous-time analog signal, whereby the second digital signal is an output signal of the analog delta-sigma modulator.
2. The method according to claim 1 , wherein said step (e) comprises the steps of:
(i) generating a third digital signal representative of the at least a portion of the digitally processed first digital signal, the third digital signal having the first throughput rate; and
(ii) converting the third digital signal to the continuous-time analog feedback signal.
3. The method according to claim 2 , wherein the second digital signal is substantially similar to the third digital signal.
4. The method according to claim 1 , wherein the first digital signal is a multi-bit digital signal.
5. The method according to claim 1 , wherein said step (d) comprises the step of applying digital dither to the first digital signal.
6. The method according to claim 5 , wherein the first digital signal is an in-bit digital signal and said step (d) further comprises the steps of alternately outputting different sets of n-bits from the in-bit first digital signal as a digitally dithered feedback signal, wherein m is greater than n.
7. The method according to claim 5 , wherein the first digital signal is an m-bit digital signal and said step (d) further comprises the steps of randomly selecting different sets of n-bits from the n-bit first digital signal to output as a digitally dithered feedback signal, wherein m is greater than n.
8. The method according to claim 1 , wherein said step (d) comprises the step of processing the first digital signal with a shuffler circuit.
9. The method according to claim 1 , wherein said step (d) comprises the step of processing the first digital signal with a dynamic element mismatch circuit.
10. The method according to claim 1 , wherein the second digital signal is substantially similar to the first digital signal.
11. The method according to claim 1 , wherein the second digital signal is generated from the first digital signal.
12. The method according to claim 1 , wherein the second throughput rate is higher than the first throughput rate.
13. The method according to claim 1 , wherein the second throughput rate is lower than the first throughput rate.
14. A method for performing feedback processing in analog delta-sigma modulators, comprising the steps of:
(a) receiving an analog signal from a first path of a delta-sigma modulator;
(b) converting the received analog signal to a higher throughput rate digital signal;
(c) digitally processing the higher throughput rate digital signal in a pipeline, whereby samples of the higher throughput rate digital signal sequentially pass through a plurality of stages of the pipeline at the higher throughput rate;
(d) converting the digitally processed higher throughput rate digital signal to a lower throughput rate analog feedback signal;
(e) providing the analog feedback signal to a second path of the delta-sigma modulator; and
(f) generating a second digital signal representative of the received analog signal, whereby the second digital signal is an output signal of the analog delta-sigma modulator.
15. The method according to claim 14 , wherein the higher throughput rate digital signal is a multi-bit digital signal.
16. The method according to claim 14 , wherein said step (c) comprises the step of applying digital dither to the first digital signal.
17. The method according to claim 16 , wherein the higher throughput rate digital signal is an in-bit digital signal and said step (c) further comprises the steps of alternately outputting different sets of n-bits from the in-bit digital signal as a digitally dithered feedback signal, wherein m is greater than n.
18. The method according to claim 16 , wherein the higher throughput rate digital signal is an in-bit digital signal and said step (c) further comprises the steps of randomly selecting different sets of n-bits from the in-bit digital signal to output as a digitally dithered feedback signal, wherein in is greater than n.
19. The method according to claim 14 , wherein said step (c) comprises the step of processing the higher throughput rate digital signal with a shuffler circuit.
20. The method according to claim 14 , wherein said step (c) comprises the step of processing the higher throughput rate digital signal with a dynamic element mismatch circuit.