IP Library › Granted Patent US 8,054,089
Granted Patent B2
US 8,054,089 · App. 11/915,183 · Granted Nov 8, 2011

Capacitance measuring circuit

Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.v.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,054,089
App. No.
11/915,183
Granted
Nov 8, 2011
Kind
B2
Abstract

The present invention is based on the finding that a capacitance can be measured precisely and efficiently when, in a delta-sigma modulator having an operational amplifier, a first capacitor connectable to an input of the operational amplifier, and a second capacitor in a feedback branch of the operational amplifier, a reference signal source is connectable to the first capacitor, wherein the first or second capacitor may represent a capacitance to be measured. Due to the fact that, in contrast to what is conventional, no input quantity is measured and digitalized at the input of the delta-sigma modulator, but instead a defined reference signal source is coupled at the input and a device of the delta-sigma modulator itself represents the measuring quantity, an extremely compact circuit is provided allowing capacitances to be measured quickly and reliably, the measuring result being additionally made available in a digital form.

Claims (11)

1. A capacitance measuring circuit operated in a clocked manner, comprising:

a delta-sigma modulator in differential structure comprising an operational amplifier comprising differential outputs, and a first variable capacitor connected in a first clock with a first terminal to the inverting input and with a second terminal to the non-inverting input of the operational amplifier; and

a first reference signal source connected in a second clock to the first terminal of the first variable capacitor and a second reference signal source connected in the second clock to the second terminal of the first variable capacitor; wherein

the first variable capacitor represents a capacitance to be measured; and

a signal processing device is coupled to the differential outputs of the operational amplifier and is arranged to generate a digital bit stream.

2. The capacitance measuring circuit according to claim 1 , wherein the first reference signal source is implemented to provide a reference voltage, and wherein the second reference signal source is implemented to provide a reference voltage comprising the same magnitude as the first reference signal source but a different sign.

3. The capacitance measuring circuit according to claim 1 , wherein the capacitance measuring circuit additionally comprises an offset signal source connectable to the inverting and the non-inverting input of the operational amplifier to provide a constant offset capacitance to compensate for a static portion of the capacitance of the first variable capacitor.

4. The capacitance measuring circuit according to claim 3 , wherein the offset signal source comprises a second capacitor connected in the first clock with a first terminal to the inverting input and with a second terminal to the non-inverting input of the operational amplifier; wherein

the second capacitor is connected in the second clock with the first terminal to the second reference signal source and with the second terminal to the first reference signal source.

5. The capacitance measuring circuit according to claim 1 , wherein a first balance signal source is connectable to the inverting input and a second balance signal source to the non-inverting input of the operational amplifier for providing a positive and a negative balance signal.

6. The capacitance measuring circuit according to claim 5 , wherein the first and second balance signal sources each comprise another capacitor connected to the first reference signal source or to the second reference signal source by a respective switch, wherein the switches are controlled by the digital bit stream output from the signal processing device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2007
From: HAUER, JOHANN; MOEDL, STEFAN; HARTMANN, MARCUS
To: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Reel/Frame 020277/0757 →
Priority Claims (2)
DE 10 2005 024 098 · May 25, 2005 · national
DE 10 2005 038 875 · Aug 17, 2005 · national
Continuity (1)
Related Publication 20080191713A1 · Aug 14, 2008