Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback
A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay.
1. A delta-sigma modulator comprising:
a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function;
a second summing point adding an output signal from said transfer function to said input signal and subtracting a second feedback signal;
a first integrator receiving an output signal from said second summing point;
a quantizer receiving an output signal from said integrator and generating an output bitstream;
a digital-to-analog converter receiving said bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay,
wherein the delta-sigma modulator operates with a charge phase and a transfer phase and quantization is performed in the transfer phase.
2. The delta-sigma modulator according to claim 1 , wherein the digital-to-analog converter (DAC) is implemented by two charge-transfer DACs each configured to delay a generated analog feedback signal by one sample.
3. The delta-sigma modulator according to claim 1 , wherein the delta-sigma modulator is oversampled.
4. The delta-sigma modulator according to claim 1 , wherein the delta-sigma modulator is an n-th order, multi-loop or multi-bit modulator.
5. An n-th order, multi-loop or multi-bit delta-sigma modulator comprising:
a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function;
a second summing point adding an output signal from said transfer function to said input signal and subtracting a second feedback signal;
a first integrator receiving an output signal from said second summing point;
a quantizer receiving an output signal from said integrator and generating an output bitstream;
a digital-to-analog converter receiving said bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay,
wherein the transfer function is provided by a second integrator generating an output signal fed to a first amplifier to via a second amplifier to a third integrator, wherein the output signal of the third integrator is amplified by a third amplifier whose output signal is added to the output signal of the first amplifier.
6. The delta-sigma modulator according to claim 1 , wherein the quantizer is a n-level multi-bit variable resolution quantizer.
7. The delta-sigma modulator according to claim 2 , wherein a charge phase is non-overlapping with a following transfer phase.
8. The delta-sigma modulator according to claim 7 , further comprising a latch signal generated at the end of the transfer phase and used to latch a signal for the quantizer.
9. The delta-sigma modulator according to claim 4 , wherein a summing point is implemented by a node connected with a first terminal of at least a first capacitor and a second capacitor, wherein the second terminals of the first and second capacitor receive charges to be added via respective switches.
10. A delta-sigma modulator comprising:
a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function;
a second summing point adding an output signal from said transfer function to said input signal and subtracting a second feedback signal;
a first integrator receiving an output signal from said second summing point;
a quantizer receiving an output signal from said integrator and generating an output bitstream;
a digital-to-analog converter receiving said bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay,
wherein the digital-to-analog converter (DAC) is a single voltage DAC followed by a one sample delay, wherein an output of the one-sample delay if coupled with the first and second summing point.
11. A method for operating a delta-sigma modulator comprising:
subtracting a first feedback signal from an input signal and forwarding a result to a transfer function;
adding an output signal from said transfer function to said input signal and subtracting a second feedback signal and integrating a resulting output signal;
quantizing the integrated signal and generating an output bitstream;
converting said bitstream into an analog signal and delaying the analog signal by a one sample delay to provide the first and second feedback signal,
wherein the method is performed with a charge phase and a transfer phase and quantization is performed in the transfer phase.
12. The method according to claim 11 , wherein a digital-to-analog conversion is implemented by two charge-transfer digital-to-analog converters (DAC) each configured to delay a generated analog feedback signal by one sample.
13. The method according to claim 11 , wherein the delta-sigma modulator is oversampled.
14. The method according to claim 12 , wherein the quantizer is a n-level multi-bit variable resolution quantizer.
15. The method according to claim 14 , wherein the transfer function is provided by a second integrator generating an output signal fed to a first amplifier to via a second amplifier to a third integrator, wherein the output signal of the third integrator is amplified by a third amplifier whose output signal is added to the output signal of the first amplifier.
16. The method according to claim 11 , wherein the step of quantizing is performed by a n-level multi-bit variable resolution quantizer.
17. The method according to claim 12 , wherein a charge phase is non-overlapping with a following transfer phase.
18. The method according to claim 17 , further comprising a latch signal generated at the end of the transfer phase and used to latch a signal for the quantizer.
19. The method according to claim 15 , wherein the step of adding is implemented by a node connected with a first terminal of at least a first capacitor and a second capacitor, wherein the second terminals of the first and second capacitor receive charges to be added via respective switches.
20. The method according to claim 11 , wherein converting said bitstream is performed by a single voltage DAC followed by a one sample delay, wherein an output of the one-sample delay if coupled with the first and second summing point.