IP Library › Granted Patent US 8,947,279
Granted Patent B2
US 8,947,279 · App. 14/178,012 · Granted Feb 3, 2015

Delta/sigma modulator

Inventors: Daiki Ono (Yokohama, JP); Jun Deguchi (Kawasaki, JP)
Assignee: Kabushiki Kaisha Toshiba
H03M3/30H03M1/12H03M7/30H03M1/00
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Quick Facts
Patent No.
US 8,947,279
App. No.
14/178,012
Granted
Feb 3, 2015
Kind
B2
Abstract

According to one embodiment, a delta/sigma modulator includes a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage, a second multiplier based on a second variable capacitor having capacitance C S2 and a third variable capacitor having capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path, and an adder configured to add an output of the first multiplier and an output of the second multiplier, wherein C S1 , C S2 and C S3 are the same.

Claims (57)

1. A delta/sigma modulator comprising:

a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having first variable capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage;

a second multiplier based on a second variable capacitor having second variable capacitance C S2 and a third variable capacitor having third variable capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path; and

an adder configured to add an output of the first multiplier and an output of the second multiplier, wherein

the first variable capacitance C S1 , the second variable capacitance C S2 , and the third variable capacitance C S3 are the same.

2. The modulator of claim 1 , wherein the reference capacitor, the first variable capacitor, the second variable capacitor, and the third variable capacitor are provided on the same substrate.

3. The modulator of claim 1 , wherein an output voltage of the modulator varies in proportion to pressure applied to an upper electrode of each of the first, second, and third variable capacitors.

4. The modulator of claim 1 , wherein the adder subtracts an output value of the second multiplier from an output value of the first multiplier.

5. The modulator of claim 1 , wherein the first, second, and third variable capacitors are MEMS elements.

6. A delta/sigma modulator comprising:

a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having first variable capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage;

a second multiplier based on a second variable capacitor having second variable capacitance C S2 and a third variable capacitor having third variable capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path;

an adder configured to add an output of the first multiplier and an output of the second multiplier;

an integrator coupled to an output of the adder;

a comparator coupled to an output of the integrator; and

a delay element provided in a feedback path and coupled between an output of the comparator and an input of the second multiplier, wherein

the first variable capacitance C S1 , the second variable capacitance C S2 , and the third variable capacitance C S3 are the same.

7. The modulator of claim 6 , wherein the reference capacitor, the first variable capacitor, the second variable capacitor, and the third variable capacitor are provided on the same substrate.

8. The modulator of claim 6 , wherein an output voltage of the modulator varies in proportion to pressure applied to an upper electrode of each of the first, second, and third variable capacitors.

9. The modulator of claim 6 , wherein the adder subtracts an output value of the second multiplier from an output value of the first multiplier.

10. The modulator of claim 6 , wherein the first, second, and third variable capacitors are MEMS elements.

11. A delta/sigma modulator comprising:

a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having first variable capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage;

a second multiplier based on a second variable capacitor having second variable capacitance C S2 and a third variable capacitor having third variable capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path;

a first adder configured to add an output of the first multiplier and an output of the second multiplier;

a first integrator coupled to an output of the first adder;

a third multiplier coupled to an output of the first integrator and defined by a multiplier factor 1;

a fourth multiplier provided in a branch path of the feedback path and defined by a multiplier factor 1;

a second adder configured to add an output of the third multiplier and an output of the fourth multiplier;

a second integrator coupled to an output of the second adder;

a comparator coupled to an output of the second integrator; and

a delay element provided in the feedback path, coupled between an output of the comparator and an input of the second multiplier, and coupled between the output of the comparator and an input of the fourth multiplier, wherein

the first variable capacitance C S1 , the second variable capacitance C S2 , and the third variable capacitance C S3 are the same.

12. The modulator of claim 11 , wherein the reference capacitor, the first variable capacitor, the second variable capacitor, and the third variable capacitor are provided on the same substrate.

13. The modulator of claim 11 , wherein an output voltage of the modulator varies in proportion to pressure applied to an upper electrode of each of the first, second, and third variable capacitors.

14. The modulator of claim 11 , wherein the first adder subtracts an output value of the second multiplier from an output value of the first multiplier.

15. The modulator of claim 11 , wherein the first, second, and third variable capacitors are MEMS elements.

16. A delta/sigma modulator comprising:

a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having first variable capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage;

a second multiplier based on a second variable capacitor having second variable capacitance C S2 and a third variable capacitor having third variable capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and provided in a feedback path;

a first adder configured to add an output of the first multiplier and an output of the second multiplier;

a first integrator coupled to an output of the first adder;

a third multiplier coupled to an output of the first integrator and defined by a multiplier factor 1;

a fourth multiplier provided in a first branch path of the feedback path and defined by a multiplier factor 1;

a second adder configured to add an output of the third multiplier and an output of the fourth multiplier;

a second integrator coupled to an output of the second adder;

a fifth multiplier coupled to an output of the second integrator and defined by a multiplier factor 1;

a sixth multiplier provided in a second branch path of the feedback path and defined by a multiplier factor 1;

a third adder configured to add an output of the fifth multiplier and an output of the sixth multiplier;

a third integrator coupled to an output of the third adder;

a comparator coupled to an output of the third integrator; and

a delay element provided in the feedback path, coupled between an output of the comparator and an input of the second multiplier, coupled between the output of the comparator and an input of the fourth multiplier, and coupled between the output of the comparator and an input of the sixth multiplier, wherein

the first variable capacitance C S1 , the second variable capacitance C S2 , and the third variable capacitance C S3 are the same.

17. The modulator of claim 16 , wherein the reference capacitor, the first variable capacitor, the second variable capacitor, and the third variable capacitor are provided on the same substrate.

18. The modulator of claim 16 , wherein an output voltage of the modulator varies in proportion to pressure applied to an upper electrode of each of the first, second, and third variable capacitors.

19. The modulator of claim 16 , wherein the first adder subtracts an output value of the second multiplier from an output value of the first multiplier.

20. The modulator of claim 16 , wherein the first, second, and third variable capacitors are MEMS elements.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2014
From: ONO, DAIKI; DEGUCHI, JUN
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 032250/0559 →
Priority Claims (1)
JP 2013-141779 · Jul 5, 2013 · national
Continuity (1)
Related Publication 20150009054A1 · Jan 8, 2015