Apparatus and method for clock generation with piecewise linear modulation

1. An apparatus for generating a clock using piecewise linear modulation, comprising:

a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile including two or more linear signals;

a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M;

a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock;

a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses;

a loop filter for outputting a control voltage corresponding to the predetermined current;

a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; and

a fractional divider for receiving the multi-phase clock of the VCO, selecting a divider according to the K-bit profile, and outputting a divided clock as the feedback clock signal, by interpolating phases of the multi-phase clock, the fractional divider including

a division controller for outputting a selection signal according to the K-bit profile of the delta-sigma modulator and the feedback clock,

a phase selector for selecting a clock signal from the multi-phase clock according to the selection signal, and

a phase interpolator for interpolating the selected clock signal according to the selection signal to generate a divided clock, wherein the phase selector includes

an edge detector for detecting an edge of the output of the division controller,

a sampling synchronizer for synchronizing the multi-phase clock with the detected edge, and

a multiplexer for selecting the clock signal from the multi-phase clock and dividing the frequency of the multi-phase clock.

2. The apparatus of claim 1 , wherein the modulation profile generator comprises:

an accumulator controller for outputting an accumulator control signal corresponding to the piecewise linear modulation profile; and

an accumulator for outputting the M-bit digital profile obtained by adding or subtracting a value according to the accumulator control signal to/from a previous output.

3. The apparatus of claim 1 , wherein the piecewise linear modulation profile comprises maximums, minimums and sectional inclinations of the linear signals.

4. The apparatus of claim 1 , wherein the modulation profile generator has a Pseudo Random Bit Sequence (PRBS) therein.

5. The apparatus of claim 1 , wherein clock gating technology is applied to the modulation profile generator.

6. A method of generating a clock using piecewise linear modulation, comprising:

outputting, by a modulation profile generator, an M-bit digital profile obtained by quantizing a piecewise linear modulation profile including two or more linear signals;

receiving, by a delta-sigma modulator, the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M;

outputting, by a phase-frequency comparator, up and down pulses having the same phase difference as that between a reference clock and a feedback clock;

outputting, by a charge pump, a predetermined current for a time corresponding to the phase difference between the up and down pulses;

outputting, by a loop filter, a control voltage corresponding to the predetermined current;

outputting, by a voltage controlled oscillator (VCO), a multi-phase clock having a frequency corresponding to a level of the control voltage; and

receiving, by a fractional divider, the multi-phase clock, selecting a divider according to the K-bit profile, and applying a divided clock as the feedback clock by interpolating phases of the multi-phase clock, the applying further including

outputting, by a division controller, a selection signal according to the K-bit profile of the delta-sigma modulator and the feedback clock,

selecting, by a phase selector, a clock signal from the multi-phase clock according to the selection signal, and

interpolating, by a phase interpolator, the selected clock signal according to the selection signal to generate a divided clock, wherein the selecting by the phase selector includes

detecting, by an edge detector, an edge of the output of the division controller,

synchronizing, by a sampling synchronizer, the multi-phase clock with the detected edge,

selecting, by a multiplexer, the clock signal from the multi-phase clock, and

dividing, by the multiplexer, the frequency of the multi-phase clock.