Delta-sigma modulator
An object is to provide a stable delta-sigma modulator having good microlevel signal reproducibility and capable of outputting a 1-bit PDM signal with a low oversampling ratio of about 64 times at a high duty ratio of 90% or more. The delta-sigma modulator has a higher-order loop filter; a first 1-bit quantizer for making a decision as to the output of the higher-order loop filter; a first feedback component for feeding the first output signal back to the input stage of the higher-order loop filter; a second 1.5-bit quantizer for making a decision as to the output absolute value of an internal stage to be monitored; a second dynamic feedback component for feeding a second output signal back to the input stage of the higher-order loop filter; and an operational unit for producing a 1-bit PDM signal Y by performing operation on the first output signal and second output signal.
1. A delta-sigma modulator comprising:
a higher-order loop filter having a plurality of internal stages and receiving an analog input signal;
a 1-bit quantizer for making a decision as to whether output of the higher-order loop filter is positive or negative with respect to an analog reference potential, and for outputting a first output signal Y 1 ;
a first feedback component for carrying out D/A conversion of the first output signal Y 1 to a negative or positive full scale level of the analog input signal, and for feeding it back to an input stage of the higher-order loop filter;
a 1.5-bit quantizer for making a decision that an output value of a prescribed internal stage of the plurality of the internal stages, inclusive of the polarity of the output value, exceeds a predetermined reference value, and for outputting a second output signal Y 2 ;
a second feedback component for carrying out D/A conversion of the second output signal Y 2 to m times a negative or positive full scale level of the analog input signal, and for feeding it back to the input stage of the higher-order loop filter; and
an operational unit for generating a 1-bit PDM signal Y by performing operations on the first output signal Y 1 (+1, −1) and the second output signal Y 2 (+m, 0, −m).
2. The delta-sigma modulator as claimed in claim 1 , wherein
the higher-order loop filter is a higher-order integrator constructed by connecting two or more integrators in cascade, and wherein outputs of the plurality of integrators correspond to the plurality of internal stages constituting the higher-order loop filter.
3. The delta-sigma modulator as claimed in claim 1 , wherein
the higher-order loop filter comprises an n-order integrator constructed by connecting two or more integrators in cascade; and a component for adding outputs of the n integrators in accordance with prescribed ratios al - an, and for supplying an addition result to the 1-bit quantizer, and wherein the outputs of the n integrators correspond to n internal stages of the higher-order loop filter.
4. The delta-sigma modulator as claimed in claim 1 , wherein
the higher-order loop filter has one of a low-pass characteristic, bandpass characteristic and high-pass characteristic, each of which is composed of a plurality of operational amplifiers, and wherein outputs of the plurality of operational amplifiers correspond to the plurality of internal stages constituting the higher-order loop filter.
5. The delta-sigma modulator as claimed in claim 1 , wherein
the 1.5-bit quantizer is a window comparator composed of two comparators;
the decision reference value is a positive decision reference value +Vth and a negative decision reference value −Vth with respect to the analog reference potential when the higher-order loop filter has a single end circuit configuration;
the decision reference value is a positive decision reference value +Vth and a negative decision reference value −Vth as a fully differential signal when the higher-order loop filter has a fully differential circuit configuration; and
as the second output signal Y 2 , +m is output when the prescribed internal stage output level is +Vth or more, −m is output when it is −Vth or less, and zero when it is between +Vth and −Vth.
6. The delta-sigma modulator as claimed in claim 1 , wherein
the prescribed internal stage in the higher-order loop filter is the most effective internal stage for a loop stability or for circumventing overload, and is a single internal stage or a result of adding outputs of the plurality of internal stages at prescribed ratios.
7. The delta-sigma modulator as claimed in claim 1 , wherein
the first output signal Y 1 is a 1-bit PDM signal intended to take +1 or −1, and the second output signal Y 2 is a 1.5-bit PDM signal intended to take +m or −m or 0, and wherein
the second output signal Y 2 is temporarily stored in the operational unit, is added to the first output signal Yl in accordance with the polarity and gain m of the second output signal Y 2 when an opposite polarity signal appears in the first output signal Yl, and is output to the PDM signal Y.
8. The delta-sigma modulator as claimed in claim 7 , wherein
the feedback gain m from the 1.5-bit quantizer is an integer normally, and unless it is an integer, the feedback gain m undergoes correction by the operational unit before the 1-bit PDM signal Y is output.