Semiconductor devices having interconnection structure

1. A semiconductor device comprising:

an etch stop layer on a lower structure that comprises a contact structure;

a buffer layer on the etch stop layer;

an intermetal insulating layer on the buffer layer, the intermetal insulating layer comprising a low-k dielectric material and comprising a first region having a first dielectric constant and a second region having a second dielectric constant that is different from the first dielectric constant, and the intermetal insulating layer being a single layer; and

an interconnection structure having a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion, the first region of the intermetal insulating layer being spaced apart from the interconnection structure,

wherein the plug portion comprises a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion, and

wherein the interconnection portion comprises opposing lateral surfaces surrounded by the intermetal insulating layer.

2. The semiconductor device of claim 1 , wherein the second region of the intermetal insulating layer is between the first region of the intermetal insulating layer and the interconnection structure.

3. The semiconductor device of claim 2 , wherein the second dielectric constant of the second region of the intermetal insulating layer is greater than the first dielectric constant of the first region of the intermetal insulating layer.

4. The semiconductor device of claim 1 , wherein the buffer layer comprises an insulating material having a third dielectric constant that is greater than the first dielectric constant of the first region of the intermetal insulating layer and the second dielectric constant of the second region of the intermetal insulating layer.

5. The semiconductor device of claim 1 , wherein the buffer layer has a thickness greater than a thickness of the etch stop layer.

6. The semiconductor device of claim 1 , wherein the etch stop layer comprises an insulating nitride having an etching selectivity with respect to both the buffer layer and the intermetal insulating layer.

7. The semiconductor device of claim 1 , wherein the opposing lateral surfaces of the interconnection portion are aligned with lateral surfaces of the plug portion in a vertical direction.

8. The semiconductor device of claim 1 , wherein the first region of the intermetal insulating layer comprises a first pore, and

wherein the second region of the intermetal insulating layer comprises a second pore that is smaller than the first pore.

9. The semiconductor device of claim 1 , wherein the plug portion comprises a third portion extending through the buffer layer, and

wherein the third portion has a width different from at least one of the width of the first portion and the width of the second portion.

10. The semiconductor device of claim 1 , wherein the interconnection portion has an uppermost surface that is coplanar with an uppermost surface of the intermetal insulating layer.

11. A semiconductor device comprising:

an etch stop layer on a lower structure;

an intermetal insulating layer on the etch stop layer, the intermetal insulating layer comprising a low-k dielectric material; and

a first interconnection structure and a second interconnection structure adjacent to each other,

wherein the intermetal insulating layer comprises a first region that is spaced apart from the first and second interconnection structures and has a first dielectric constant, and second regions that contact the first and second interconnection structures and have a second dielectric constant different from the first dielectric constant of the first region,

wherein the first interconnection structure comprises a first plug portion and a first interconnection portion on the first plug portion, and the second interconnection structure comprises a second plug portion and a second interconnection portion on the second plug portion,

wherein each of the first plug portion and the second plug portion comprises a lower portion contacting the etch stop layer and an upper portion contacting the intermetal insulating layer, and

wherein a distance between respective sidewalls of the lower portions of the first plug portion and the second plug portion is greater than a distance between respective sidewalls of the upper portions of the first plug portion and the second plug portion.

12. The semiconductor device of claim 11 , further comprising:

a buffer layer that is between the intermetal insulating layer and the etch stop layer and has a thickness greater than a thickness of the etch stop layer,

wherein the buffer layer comprises an insulating material having a third dielectric constant that is greater than the first and second dielectric constants of the first region and second regions of the intermetal insulating layer respectively.

13. The semiconductor device of claim 11 , wherein the second dielectric constant of the second regions of the intermetal insulating layer is greater than the first dielectric constant of the first region of the intermetal insulating layer.

14. The semiconductor device of claim 11 , wherein the first region of the intermetal insulating layer comprises first pores, and the second regions of the intermetal insulating layer comprise second pores that have an average size smaller than an average size of the first pores.

15. The semiconductor device of claim 11 , wherein the lower structure comprises an interlayer insulating layer and contact structures that extend through the interlayer insulating layer and contact the first plug portion and the second plug portion, respectively, and

wherein the lower portions of the first plug portion and the second plug portion have a width less than a width of upper surfaces of the contact structures.

16. An integrated circuit device comprising:

an etch stop layer on a lower structure, the etch stop layer comprising an opening exposing the lower structure;

an insulating layer comprising a low-k material on the etch stop layer, the insulating layer comprising a recess, and the insulating layer comprising a first portion that defines the recess and has a first dielectric constant and a second portion that is different from the first portion and has a second dielectric constant less than the first dielectric constant; and

a conductive structure in the recess of the insulating layer and in the opening of the etch stop layer.

17. The device of claim 16 , wherein the first portion of the insulating layer comprises first vacancies, and the second portion of the insulating layer comprises second vacancies, and

wherein an average size of the first vacancies is smaller than an average size of the second vacancies.

18. The device of claim 16 , wherein the recess comprises a lower portion and an upper portion sequentially arranged from the etch stop layer,

wherein the lower portion of the recess has a first width in a first direction, and the upper portion of the recess extends longitudinally in the first direction and has a length in the first direction that is greater than the first width of the lower portion of the recess, and

wherein the conductive structure comprises a conductive layer conformally extending on surfaces of the lower portion and the upper portion of the recess, and an uppermost surface of the conductive structure and an uppermost surface of the insulating layer are coplanar.

19. The device of claim 18 , wherein the opening of the etch stop layer has a second width in the first direction that is less than the first width of the lower portion of the recess.

20. The device of claim 16 , wherein the recess comprises a lower portion and an upper portion sequentially arranged from the etch stop layer,

wherein the lower portion of the recess has a width in a first direction, and the upper portion of the recess extends longitudinally in the first direction and has a length in the first direction that is greater than the width of the lower portion of the recess,

wherein the conductive structure comprises a plug portion in the lower portion of the recess and an interconnection portion in the upper portion of the recess, and

wherein the first portion of the insulating layer surrounds the plug portion of the conductive structure and extends on a lower surface and a side of the interconnection portion of the conductive structure.