Memory elements having conductive cap layers and methods therefor
View Patent ↗A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.
1. A memory element comprising:
a first electrode;
at least one switching layer formed over the first electrode;
a second electrode layer; and
at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein
the at least one switching layer is programmable between different impedance states by application of electric fields via the first electrode and the second electrode layer,
the at least one conductive cap layer comprises at least one amorphous layer and a further layer having grain boundaries.
2. The memory element of claim 1 , wherein the at least one amorphous layer includes a layer of an amorphous silicide.
3. The memory element of claim 1 , wherein the at least one amorphous layer includes a layer of a mictamict alloy.
4. The memory element of claim 1 , wherein the at least one amorphous layer has the composition M x Se y Q z where M is an early transition metal, Se is a semiconductor or semimetal, and Q is nitrogen or oxygen.
5. The memory element of claim 4 , wherein the M is selected from the group of: scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W) and lanthanum (La).
6. The memory element of claim 4 , wherein the Se is selected from the group of: silicon (Si), germanium (Ge) and boron (B).
7. The memory element of claim 1 , further including:
the at least one amorphous layer is in contact with the second electrode layer, and
the further layer having grain boundaries is formed over the at least one amorphous layer.
8. The memory element of claim 1 , further including:
the further layer having grain boundaries is in contact with the second electrode layer, and
the at least one amorphous layer is formed over the further layer.
9. The memory element of claim 8 , further including an upper layer having grain boundaries formed over the at least one amorphous layer.
10. A memory element comprising:
a first electrode;
at least one switching layer formed over the first electrode;
a second electrode layer; and
at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein
the at least one switching layer is programmable between different impedance states by application of electric fields via the first electrode and the second electrode layer, and
the at least one conductive cap layer includes a first layer having grain boundaries in contact with a second layer having grain boundaries, and the majority of the first layer grain boundaries are not vertically aligned with the second layer grain boundaries.
11. The memory element of claim 1 , wherein the second electrode is an anode that includes at least one element that can ion conduct in the at least one switching layer.
12. A method, comprising:
forming a first electrode;
forming at least one switching layer over the first electrode that is programmable between different impedance states by application of electric fields;
forming a second electrode layer; and
forming at least one conductive cap layer over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein
the at least one switching layer is programmable between different impedance states by application of electric fields via the first electrode and the second electrode layer, and
forming the at least one conductive cap layer includes
forming a layer having grain boundaries, and
forming at least one amorphous layer.
13. The method of claim 12 , wherein forming at least one amorphous layer includes forming a layer of a mictamict alloy.
14. The method of claim 13 , wherein the mictamict alloy has the composition M x Si y Q z where M is an early transition metal, Si is silicon, and Q is nitrogen or oxygen.
15. The method of claim 14 , wherein forming the layer of the mictamict alloy includes reactive sputtering the M and Si component with a gas that includes the Q component.
16. The method of claim 12 , wherein the location of the amorphous layer is selected from: over the layer having grain boundaries and under the layer having grain boundaries.
17. A method, comprising:
forming a first electrode;
forming at least one switching layer over the first electrode that is programmable between different impedance states by application of electric fields;
forming a second electrode layer; and
forming at least one conductive cap layer over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein
the at least one switching layer is programmable between different impedance states by application of electric fields via the first electrode and the second electrode layer, and
forming the at least one conductive cap layer includes
forming a first layer having grain boundaries over and in contact with the second electrode layer, and
forming a second layer having grain boundaries over and in contact with the first layer with a processing step separate from that which forms the first layer; wherein
the majority of the first layer grain boundaries are not vertically aligned with the second layer grain boundaries.