Integrated circuit filler and method thereof
Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
1. A method of semiconductor device fabrication, comprising:
identifying at least one gap among a plurality of functional cells;
inserting at least one standard filler cell and a pre-designed filler cell within the at least one gap, wherein the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode;
patterning a layer on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate; and
inspecting the patterned layer using an electron beam (e-beam) inspection process.
2. The method of claim 1 , further comprising:
identifying at least one of an existing failure mode and a potential failure mode in at least one functional cell of the plurality of functional cells; and
inserting the pre-designed filler cell, wherein the pattern of the layout design of the pre-designed filler cell is associated with the at least one of the existing failure mode and the potential failure mode.
3. The method of claim 2 , wherein the at least one functional cell is adjacent to the pre-designed filler cell placed within the at least one gap.
4. The method of claim 2 , further comprising:
based on the identified at least one of the existing failure mode and the potential failure mode, selecting the pre-designed filler cell prior to inserting the pre-designed filler cell.
5. The method of claim 1 , further comprising:
as part of a physical design flow, inserting the pre-designed filler cell after a floorplanning step and as part of a placement step.
6. The method of claim 1 , further comprising:
prior to inserting the pre-designed filler cell, identifying a standard filler cell within the at least one gap;
removing the standard filler cell from the at least one gap; and
inserting the pre-designed filler cell.
7. The method of claim 1 , wherein the pattern of the layout design of the pre-designed filler cell includes a repeated pattern array.
8. The method of claim 1 , further comprising:
inspecting both of the at least one standard filler cell and the pre-designed filler cell using the e-beam inspection process, wherein a first analysis cycle time for inspection of the pre-designed filler cell is less than a second analysis cycle time for inspection of the standard filler cell.
9. The method of claim 1 , further comprising:
patterning the layer, wherein the patterning the layer includes:
fabricating a mask including the pattern of the layout design of the pre-designed filler cell;
transferring, by way of a photolithography process, the pattern of the layout design from the mask to the layer on the semiconductor substrate.
10. A method of semiconductor device fabrication, comprising:
identifying a standard filler cell disposed in a gap between a plurality of functional cells;
removing the standard filler cell and inserting a redesigned filler cell within the gap between the plurality of functional cells, wherein the redesigned filler cell includes a layout pattern associated with a particular failure mode;
patterning a substrate layer such that the layout pattern is transferred to the substrate layer; and
inspecting the patterned layer.
11. The method of claim 10 , wherein the standard filler cell includes an irregular pattern, and wherein the redesigned filler cell includes a repeated array.
12. The method of claim 10 , further comprising:
identifying at least one of an existing failure mode and a potential failure mode in at least one functional cell of the plurality of functional cells;
selecting the redesigned filler cell having the layout pattern associated with the at least one of the existing failure mode and the potential failure mode; and
after removing the standard filler cell, inserting the selected redesigned filler cell.
13. The method of claim 12 , wherein the at least one functional cell is adjacent to the selected redesigned filler cell.
14. The method of claim 10 , wherein the removing the standard filler cell and inserting the redesigned filler cell is performed as part of at least one of a floorplanning step and a placement step of a physical design flow.
15. The method of claim 10 , further comprising:
patterning the substrate layer, wherein the patterning the substrate layer includes:
fabricating a mask including the layout pattern of the redesigned filler cell;
transferring, by way of a photolithography process, the layout pattern from the mask to the substrate layer.
16. The method of claim 10 , wherein the inspecting the patterned layer includes inspecting the patterned layer using an electron beam (e-beam) inspection process.
17. A method, comprising:
identifying a gap between a first functional cell and a second functional cell;
inserting a first filler cell and a second filler cell within the gap, wherein the first filler cell includes a standard filler cell and the second filler cell includes a pre-designed filler cell, wherein the standard filler cell includes an irregular pattern and the pre-designed filler cell includes a repeated array, and wherein the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode;
patterning a semiconductor substrate to include the pattern of the layout design; and
performing an electron-beam inspection of the patterned semiconductor substrate.
18. The method of claim 17 , further comprising:
identifying at least one of an existing failure mode and a potential failure mode in at least one of the first functional cell and the second functional cell; and
inserting the pre-designed filler cell, wherein the pattern of the layout design of the pre-designed filler cell is associated with the at least one of the existing failure mode and the potential failure mode.
19. The method of claim 18 , wherein the at least one of the first functional cell and the second functional cell is adjacent to the pre-designed filler cell placed within the gap.
20. The method of claim 17 , wherein the performing the electron-beam inspection further includes inspecting both of the standard filler cell and the pre-designed filler cell, wherein a first analysis cycle time for inspection of the pre-designed filler cell is less than a second analysis cycle time for inspection of the standard filler cell.