Power module package having patterned insulation metal substrate
A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.
1. A packaging structure, comprising:
a substrate including a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer;
a first chip disposed on the metal carrier not covered by the patterned insulation layer;
a second chip disposed on the patterned conductive layer and electrically connected to the first chip by a conductive unit comprising one or more clip bonds, one or more redistribution layer (RDL) structures comprising at least one wiring layer and at least one insulation layer stacked over one another, or a combination thereof; and
an encapsulating material surrounding the substrate, the first chip, the second chip, and the conductive unit, wherein a portion of the conductive unit is exposed from the encapsulating material.
2. The packaging structure as claimed in claim 1 , wherein each of the clip bonds and the redistribution layer structures is electrically connected to at least two of the first chip, the second chip, and the substrate.
3. The packaging structure as claimed in claim 1 , wherein the substrate comprises a protrusion projecting toward and electrically connected to the conductive unit.
4. The packaging structure as claimed in claim 3 , wherein the protrusion of the substrate comprises a portion of the patterned insulation layer, and a portion of the patterned conductive layer disposed on the portion of the patterned insulation layer.
5. The packaging structure as claimed in claim 3 , wherein the protrusion of the substrate is located between the first chip and the second chip.
6. The packaging structure as claimed in claim 3 , wherein the conductive unit comprises a leg portion electrically connected to the protrusion.
7. The packaging structure as claimed in claim 1 , wherein the conductive unit comprises a leg portion which is bent toward and electrically connected to the substrate.
8. The packaging structure as claimed in claim 7 , wherein the leg portion is located between the first chip and the second chip.
9. The packaging structure as claimed in claim 7 , wherein the leg portion is located away from a region between the first chip and the second chip.
10. The packaging structure as claimed in claim 1 , wherein the metal carrier comprises a cavity, a recess or a slot, and the first chip is disposed in the cavity, the recess or the slot.
11. The packaging structure as claimed in claim 1 , wherein the metal carrier comprises an opening, and the first chip is disposed in the opening.
12. The packaging structure as claimed in claim 1 , wherein the patterned insulation layer comprises a first portion covered by a portion of the patterned conductive layer, and the second chip is disposed on the portion of the patterned conductive layer.
13. The packaging structure as claimed in claim 1 , wherein the patterned insulation layer comprises a first portion covered by a portion of the patterned conductive layer and a second portion covered by another portion of the patterned conductive layer, and the first chip is electrically connected to the another portion of the patterned conductive layer.
14. The packaging structure as claimed in claim 1 , wherein the first chip is directly connected to the metal carrier.
15. The packaging structure as claimed in claim 1 , wherein the first chip comprises a lateral semiconductor component.
16. The packaging structure as claimed in claim 1 , wherein the second chip comprises a vertical semiconductor component.
17. The packaging structure as claimed in claim 1 , wherein the first chip has an active side with electrodes thereon and a bottom side opposite to the active side, and the first chip is disposed on the metal carrier via the bottom side.