IP Library Granted Patent US 10,163,950
Granted Patent B2
US 10,163,950 · App. 15/487,283 · Granted Dec 25, 2018

Solid state imaging device and electronic apparatus

Inventors: Shoji Kobayashi (Kanagawa, JP); Yoshiharu Kudoh (Kanagawa, JP); Takuya Sano (Kanagawa, JP)
Assignee: Sony Corporation
H01L27/14623H01L27/1462H01L27/1464H01L27/14603H01L27/14605H01L27/14612H01L27/14621H01L27/14625H01L27/14627H01L27/14629H01L27/14636H01L27/14643H01L27/14645H04N5/2253H04N5/2254H04N5/369H04N5/374H01L27/14609
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,163,950
App. No.
15/487,283
Granted
Dec 25, 2018
Kind
B2
Abstract

A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit.

Claims (36)

1. An imaging device comprising:

a first semiconductor substrate including a first multilayer wiring layer at one side thereof, the first semiconductor substrate including a pixel region having a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion unit;

a second semiconductor substrate including a second multilayer wiring layer at one side thereof, the second semiconductor substrate including a logic circuit unit that includes at least one transistor, wherein the first semiconductor substrate and the second semiconductor substrate are bonded such that the first multilayer wiring layer and the second multilayer wiring layer face each other; and

a light-shielding member between the pixel region and the logic circuit unit, wherein the light-shielding member blocks an emitted light of the at least one transistor from entering the photoelectric conversion unit.

2. The imaging device according to claim 1 , wherein the light-shielding member is within the second multilayer wiring layer.

3. The imaging device according to claim 1 , wherein the light-shielding member is within the first multilayer wiring layer.

4. The imaging device according to claim 1 , wherein the light-shielding member includes wirings of both the first and the second multilayer wiring layers.

5. The imaging device according to claim 1 , wherein the light-shielding member is a wiring of the second multilayer wiring layer.

6. The imaging device according to claim 1 , wherein the light-shielding member is a wiring of the first multilayer wiring layer.

7. The imaging device according to claim 1 , wherein the light-shielding member includes a plurality of wiring layers within the first multilayer wiring layer and the second multilayer wiring layer.

8. The imaging device according to claim 1 , wherein the light-shielding member covers whole spaces which are not covered by first and second wiring layers of the first multilayer wiring layer in a plan view.

9. The imaging device according to claim 1 , further comprising a connected conductor which electrically connects the first multilayer wiring layer and the second multilayer wiring layer.

10. An electronic apparatus comprising:

an imaging device including:

a first semiconductor substrate including a first multilayer wiring layer at one side thereof, the first semiconductor substrate including a pixel region having a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion unit,

a second semiconductor substrate including a second multilayer wiring layer at one side thereof, the second semiconductor substrate including a logic circuit unit that includes at least one transistor, wherein the first semiconductor substrate and the second semiconductor substrate are bonded such that the first multilayer wiring layer and the second multilayer wiring layer face each other, and

a light-shielding member between the pixel region and the logic circuit unit, wherein the light-shielding member blocks an emitted light of the at least one transistor from entering the photoelectric conversion unit; and

a lens configured to direct light to a surface of the imaging device.

11. The electronic apparatus according to claim 10 , wherein the light-shielding member is within the second multilayer wiring layer.

12. The electronic apparatus according to claim 10 , wherein the light-shielding member is within the first multilayer wiring layer.

13. The electronic apparatus according to claim 10 , wherein the light-shielding member includes wirings of both the first and the second multilayer wiring layers.

14. The electronic apparatus according to claim 10 , wherein the light-shielding member is a wiring of the second multilayer wiring layer.

15. The electronic apparatus according to claim 10 , wherein the light-shielding member is a wiring of the first multilayer wiring layer.

16. The electronic apparatus according to claim 10 , wherein the light-shielding member includes a plurality of wiring layers within the first multilayer wiring layer and the second multilayer wiring layer.

17. The electronic apparatus according to claim 10 , wherein the light-shielding member covers whole spaces which are not covered by first and second wiring layers of the first multilayer wiring layer in a plan view.

18. The electronic apparatus according to claim 10 , further comprising a connected conductor which electrically connects the first multilayer wiring layer and the second multilayer wiring layer.

19. An imaging device comprising:

a first semiconductor substrate including a first multilayer wiring at one side thereof, the first semiconductor substrate including a pixel region having a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion unit;

a second semiconductor substrate including a second multilayer wiring layer at one side thereof, the second semiconductor substrate including a logic circuit unit that includes at least one transistor, wherein the first semiconductor substrate and the second semiconductor substrate are bonded such that the first multilayer wiring layer and the second multilayer wiring layer face each other; and

a light-shielding member between the pixel region and the logic circuit unit, wherein the light-shielding member covers whole spaces which are not covered by first and second wiring layers of the first multilayer wiring layer in a plan view.

20. An electronic apparatus comprising:

an imaging device including:

a first semiconductor substrate including a first multilayer wiring layer at one side thereof, the first semiconductor substrate including a pixel region having a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion unit,

a second semiconductor substrate including a second multilayer wiring layer at one side thereof, the second semiconductor substrate including a logic circuit unit that includes at least one transistor, wherein the first semiconductor substrate and the second semiconductor substrate are bonded such that the first multilayer wiring layer and the second multilayer wiring layer face each other, and

a light-shielding member between the pixel region and the logic circuit unit, wherein the light-shielding member covers whole spaces which are not covered by first and second wiring layers of the first multilayer wiring layer in a plan view; and

a lens configured to direct light to a surface of the imaging device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2021
From: KOBAYASHI, SHOJI; KUDOH, YOSHIHARU; SANO, TAKUYA
To: SONY CORPORATION
Reel/Frame 056986/0464 →
Priority Claims (1)
JP 2010-206890 · Sep 15, 2010 · national
Continuity (6)
Continuation 15412811 · Jan 23, 2017
Continuation 15087709 · Mar 31, 2016
Continuation 14881818 · Oct 13, 2015
Continuation 14057542 · Oct 18, 2013
Continuation 13227851 · Sep 8, 2011
Related Publication 20170287961A1 · Oct 5, 2017
Cited By (1)
US 12,243,886