Compact three-dimensional memory with semi-conductive address line portion
In a compact three-dimensional memory (3D-M C ), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
1. A compact three-dimensional memory (3D-M C ), comprising:
a semiconductor substrate with transistors thereon;
a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and
at least a contact via coupling said memory level with said semiconductor substrate;
wherein said memory array comprises:
a first address-line extending from said memory array to said above-substrate decoding stage;
a second address-line intersecting said first address-line;
a memory device located at the intersection of said first and second address-lines, said memory device comprising a diode or a diode-like device;
said above-substrate decoding stage comprises:
a control line intersecting said first address-line;
a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, said decoding device comprising a transistor or a transistor-like device;
wherein said decoding device has a conduction mode and a blocking mode: in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line; in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;
wherein said memory device and said decoding device are located on a same memory level.
2. The memory according to claim 1 , wherein said memory device is a two-terminal device.
3. The memory according to claim 1 , wherein said memory device comprises a diode layer and a programmable layer.
4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).
5. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).
6. The memory according to claim 1 , wherein said 3D-M is a three-dimensional mask-programmed read-only memory (3D-MPROM) or a three-dimensional electrically-programmable read-only memory (3D-EPROM).
7. The memory according to claim 1 , wherein said decoding device is a three-terminal device.
8. The memory according to claim 1 , wherein said decoding device comprises a pass-transistor.
9. The memory according to claim 1 , wherein said decoding device comprises a MOSFET.
10. The memory according to claim 1 , wherein said decoding device comprises a JFET.
11. A compact three-dimensional memory (3D-M C ), comprising:
a semiconductor substrate with transistors thereon;
a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and
at least a contact via coupling said memory level with said semiconductor substrate;
wherein said memory array comprises:
a first address-line extending from said memory array to said above-substrate decoding stage;
a second address-line intersecting said first address-line;
a memory device located at the intersection of said first and second address-lines, wherein the overlap portion and the non-overlap portions of said first address-line with said second address-line have the same electrical characteristics;
said above-substrate decoding stage comprises:
a control line intersecting said first address-line;
a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, wherein the overlap portion and the non-overlap portions of said first address-line with said control line have different electrical characteristics;
wherein said decoding device has a conduction mode and a blocking mode: in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line; in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;
wherein said memory device and said decoding device are located on a same memory level.
12. The memory according to claim 11 , wherein the overlap portion and the non-overlap portions of said first address-line with said second address-line are both highly-conductive.
13. The memory according to claim 11 , wherein said memory device comprises a diode or a diode-like device.
14. The memory according to claim 11 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).
15. The memory according to claim 11 , wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).
16. The memory according to claim 11 , wherein
the overlap portion of said first address-line with said control line is semi-conductive; and,
the non-overlap portions of said first address-line with said control line are highly-conductive.
17. The memory according to claim 11 , wherein said decoding device comprises a transistor or a transistor-like device.
18. The memory according to claim 11 , wherein said decoding device comprises a pass-transistor.
19. The memory according to claim 11 , wherein said decoding device comprises a MOSFET.
20. The memory according to claim 11 , wherein said decoding device comprises a JFET.