Package substrate with embedded noise shielding walls
View Patent ↗A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W 1 and a right shielding wall W 2 . The signal line S, left shielding wall W 1 , and the right shielding wall W 2 are embedded in a dielectric layer.
1. A package substrate with embedded noise shielding walls, comprises:
a first signal line, embedded in a first dielectric layer;
a left shielding wall, embedded in the first dielectric layer and configured on a left side of the first signal line, wherein the left shielding wall extents upwards to have a top surface higher than a top surface of the first signal line;
a right shielding wall, embedded in the first dielectric layer and configured on a right side of the first signal line, wherein the right shielding wall extents upwards to have a top surface higher than the top surface of the first signal line;
a bottom shielding wall, configured on bottom sides of the left shielding wall and the right shielding wall, wherein the left shielding wall, the right shielding wall, and the bottom shielding wall are electrically coupled to ground; and
a top metal wall, configured on top sides of the left shielding wall and the right shielding wall, wherein the top shielding wall, the left shielding wall, the right shielding wall and the bottom shielding wall can form a four-sided closed structure, and the first signal line is disposed in the four-sided closed structure.
2. A package substrate with embedded noise shielding walls as claimed in claim 1 , wherein
the left shielding wall having a bottom surface no higher than a bottom surface of the first signal line; and
the right shielding wall having a bottom surface no higher than the bottom surface of the first signal line.
3. A package substrate with embedded noise shielding walls as claimed in claim 1 , further comprising:
a redistribution layer, configured on a bottom surface of the first dielectric layer; and
a chip, configured on top of the package substrate; the chip is electrically coupled to a circuitry of the redistribution layer through a plurality of metal contacts passing through the first dielectric layer.
4. A package substrate with embedded noise shielding walls as claimed in claim 1 , further comprises:
a second signal line, embedded in the first dielectric layer, configured side by side with the first signal line;
the left shielding wall is configured on left side of the first signal line; and
the right shielding wall is configured on right side of the second signal line.
5. A package substrate with embedded noise shielding walls as claimed in claim 4 , further comprises:
a middle shielding wall, configured in between the first signal line and the second signal line.
6. A package substrate with embedded noise shielding walls as claimed in claim 4 , wherein
the left shielding wall extents upwards to have a top surface higher than a top surface of the first signal line, and
the right shielding wall extents upwards to have a top surface higher than the top surface of the first signal line.
7. A package substrate with embedded noise shielding walls as claimed in claim 6 , further comprises:
a top metal wall, configured on top sides of the left shielding wall and the right shielding wall.
8. A package substrate with embedded noise shielding walls as claimed in claim 5 , wherein
the left shielding wall extents upwards to have a top surface higher than a top surface of the first signal line,
the middle shielding wall extents upwards to have a top surface higher than the top surface of the first signal line; and
the right shielding wall extents upwards to have a top surface higher than the top surface of the first signal line.
9. A package substrate with embedded noise shielding walls as claimed in claim 8 , further comprises:
a top metal wall, configured on top sides of the left shielding wall, middle shielding wall, and the right shielding wall.