Forming transistor by selectively growing gate spacer
A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
1. A method comprising:
forming a first gate dielectric layer on a first semiconductor fin;
forming a first gate electrode over the first gate dielectric layer, wherein the first gate electrode extends on sidewalls and a top surface of the first semiconductor fin;
selectively depositing a first gate spacer on a sidewall of the first gate electrode, wherein an exposed portion of the first gate dielectric layer is free from a same material for forming the first gate spacer deposited thereon;
etching the first gate dielectric layer using the first gate spacer as an etching mask to expose a portion of the first semiconductor fin; and
forming a first epitaxy semiconductor region based on the first semiconductor fin.
2. The method of claim 1 further comprising, before the first gate spacer is selectively deposited, forming an inhibitor film on the first gate dielectric layer, wherein the inhibitor film is hydrophobic.
3. The method of claim 2 further comprising, after the first gate spacer is deposited, removing the inhibitor film.
4. The method of claim 1 further comprising:
before the first gate spacer is selectively deposited, pre-treating the first gate dielectric layer using an acid; and
performing a silylation process to attach bonds to the first gate dielectric layer.
5. The method of claim 4 , wherein the attached bonds comprise CH 3 functional groups.
6. The method of claim 1 further comprising:
after the first epitaxy semiconductor region is formed, removing the first gate spacer.
7. The method of claim 1 further comprising:
forming an inter-layer dielectric to cover the first gate spacer and the first epitaxy semiconductor region.
8. The method of claim 1 further comprising:
forming a second gate dielectric layer on a second semiconductor fin;
forming a second gate electrode over the second gate dielectric layer, wherein the second gate electrode extends on sidewalls and a top surface of the second semiconductor fin;
depositing a blanket mask layer on the second gate electrode;
anisotropically etching the blanket mask layer to form a second gate spacer;
etching the second gate dielectric layer and the second semiconductor fin using the second gate spacer as an etching mask to form a recess; and
forming a second epitaxy semiconductor region in the recess.
9. The method of claim 1 further comprising forming a hard mask layer over the first gate electrode, wherein when the first gate spacer is selectively deposited, no gate spacer is grown from the hard mask layer.
10. The method of claim 1 further comprising forming a pad oxide layer over the first gate electrode, wherein when the first gate spacer is deposited, the first gate spacer is further grown from the pad oxide layer.
11. A method comprising:
forming a gate dielectric layer on a semiconductor fin;
forming a gate electrode over the gate dielectric layer;
performing a pre-treatment on an exposed surface of the gate dielectric layer using an acid;
performing a silylation process on the exposed surface of the gate dielectric layer;
depositing a gate spacer to contact a sidewall of the gate electrode;
etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin; and
forming a epitaxy semiconductor region based on the semiconductor fin.
12. The method of claim 11 , wherein when the gate spacer is deposited, no gate spacer is deposited on the exposed surface of the gate dielectric layer.
13. The method of claim 11 , wherein when the pre-treatment is performed, portions of the semiconductor fin not overlapped by the gate electrode are covered by the gate dielectric layer.
14. The method of claim 11 , wherein the forming the gate dielectric layer comprises forming an oxide layer.
15. The method of claim 11 , wherein the depositing the gate spacer comprises selectively growing a silicon nitride layer.
16. A method comprising:
forming a gate stack over an oxide layer, wherein the gate stack comprises:
a gate electrode;
a pad layer over the gate electrode; and
an oxide hard mask over the pad layer, wherein the gate stack covers a first portion of the oxide layer, and wherein a second portion of the oxide layer is exposed;
selectively growing a gate spacer on exposed sidewalls of the gate electrode and the pad layer, wherein the second portion of the oxide layer remains exposed after the gate spacer is grown; and
forming a source/drain region adjacent to the gate spacer.
17. The method of claim 16 , wherein the pad layer is free from oxide therein.
18. The method of claim 16 , wherein when the gate spacer is grown, exposed sidewalls of the oxide hard mask remain exposed.
19. The method of claim 16 , wherein the gate spacer comprises silicon nitride.
20. The method of claim 16 further comprising, before the source/drain region is formed, removing the second portion of the oxide layer.