Transistors with recessed silicon cap and method forming same
A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
1. An integrated circuit device comprising:
dielectric isolation regions;
a semiconductor fin protruding higher than portions of the dielectric isolation regions on opposite sides of the semiconductor fin;
a silicon cap layer on, and directly contacting both of a top surface and sidewalls of, the semiconductor fin;
a gate stack on the silicon cap layer;
a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises an inner sidewall contacting the gate stack, and an outer sidewall opposite to the inner sidewall, wherein an edge of the silicon cap layer is recessed in a direction more toward the a center of the gate stack than the outer sidewall of the gate spacer, and wherein the edge of the silicon cap layer and the gate spacer are on a same side of the gate stack, and wherein in a top view of the gate spacer and the gate stack, the direction points from the outer sidewall to the inner sidewall, and the direction is perpendicular to a longitudinal direction of the gate spacer in the top view; and
a source/drain region contacting the semiconductor fin and the edge of the silicon cap layer.
2. The integrated circuit device of claim 1 , wherein the semiconductor fin is of n-type, and the silicon cap layer has a first germanium atomic percentage lower than a second germanium atomic percentage in the semiconductor fin.
3. The integrated circuit device of claim 1 , wherein the semiconductor fin is of a conductivity type selected from p-type or n-type, and wherein the silicon cap layer has a lower impurity concentration of the conductivity type than the semiconductor fin.
4. The integrated circuit device of claim 1 , wherein the silicon cap layer is recessed more toward the center of the gate stack than the outer sidewall of the gate spacer by a recessing distance greater than about 1 nm.
5. The integrated circuit device of claim 1 , wherein the silicon cap layer comprises:
a horizontal portion contacting the semiconductor fin to form a horizontal interface; and
vertical portions contacting the gate stack to form vertical interfaces, wherein the horizontal portion and the vertical portions comprise are same as each other.
6. The integrated circuit device of claim 1 , wherein the silicon cap layer is recessed more toward the gate stack than an interface between the semiconductor fin and the source/drain region.
7. The integrated circuit device of claim 1 , wherein the edge of the silicon cap layer is overlapped by a portion of the gate spacer, and the portion of the gate spacer is between the outer sidewall and the inner sidewall of the gate spacer.
8. The integrated circuit device of claim 1 , wherein the source/drain region contacts the silicon cap layer to form a vertical interface that comprises:
an upper portion; and
a lower portion lower than the upper portion, wherein the lower portion laterally extends beyond the outer sidewall of the gate spacer more than the upper portion.
9. An integrated circuit device comprising:
a bulk semiconductor substrate;
dielectric isolation regions in the bulk semiconductor substrate;
a semiconductor region over the bulk semiconductor substrate, wherein the semiconductor region is between, and higher than, opposing parts of the dielectric isolation regions;
a gate stack on the semiconductor region, the gate stack comprising a gate dielectric;
a gate spacer on a sidewall of the gate stack;
a silicon cap layer between, and contacting both of, the semiconductor region and the gate stack, wherein the silicon cap layer directly contacts both of a top surface and sidewalls of the semiconductor region; and
a source/drain region contacting both of the semiconductor region and the silicon cap layer, wherein the silicon cap layer forms a vertical interface with the source/drain region, and a part of the vertical interface is directly underlying the gate spacer, and is laterally recessed more toward a center of the gate stack than an outer sidewall of the gate spacer, and wherein the vertical interface comprises:
an upper portion; and
a lower portion lower than the upper portion, wherein the lower portion laterally extends beyond the outer sidewall of the gate spacer more than the upper portion.
10. The integrated circuit device of claim 9 , wherein the silicon cap layer has a lower germanium atomic percentage than the semiconductor region.
11. The integrated circuit device of claim 9 , wherein the lower portion of the vertical interface extends laterally beyond the outer sidewall of the gate spacer.
12. The integrated circuit device of claim 9 , wherein the part of the vertical interface is laterally recessed more toward the center than the outer sidewall of the gate spacer by a recessing distance greater than about 1 nm.
13. The integrated circuit device of claim 9 , wherein the part of the vertical interface is laterally recessed more toward the center than the outer sidewall of the gate spacer by a recessing distance, and wherein a ratio of the recessing distance to a thickness of the gate spacer is in a range between about 0.2 and about 1.0.
14. The integrated circuit device of claim 9 , wherein the semiconductor region has a first n-type impurity concentration, and the silicon cap layer has a second n-type impurity concentration lower than the first n-type impurity concentration, and the source/drain region is of p-type.
15. An integrated circuit device comprising:
a bulk semiconductor substrate;
dielectric isolation regions in the bulk semiconductor substrate;
a semiconductor region over the bulk semiconductor substrate, wherein the semiconductor region is between, and higher than, opposing parts of the dielectric isolation regions;
a gate stack over the semiconductor region, the gate stack comprising a gate dielectric;
a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises an inner sidewall contacting the gate stack, and an outer sidewall opposing the inner sidewall;
a silicon cap layer comprising a top portion between and directly contacting the semiconductor region and the gate stack, and sidewall portions directly contacting sidewalls of the semiconductor region, wherein a bottom surface of the top portion of the silicon cap layer contacts a top surface of the semiconductor region to form a horizontal interface, and the horizontal interface is laterally recessed from a corresponding edge of the gate dielectric in a direction, with the gate dielectric overlapping the horizontal interface, and wherein in a top view of the gate spacer and the gate stack, the direction points from the outer sidewall to the inner sidewall, and the direction is perpendicular to a longitudinal direction of the gate spacer in the top view; and
a source/drain region contacting the semiconductor region and silicon cap layer.
16. The integrated circuit device of claim 15 , wherein one of the sidewall portions of the silicon cap layer physically contacts the gate stack to form a vertical interface.
17. The integrated circuit device of claim 16 , wherein the vertical interface further comprises a portion laterally recessed from the corresponding edge of the gate dielectric.
18. The integrated circuit device of claim 16 , wherein the silicon cap layer has a lower germanium atomic percentage than the semiconductor region.
19. The integrated circuit device of claim 16 , wherein the horizontal interface is laterally recessed from the corresponding edge of the gate dielectric by a recessing distance greater than about 1 nm.
20. The integrated circuit device of claim 15 , wherein the source/drain region contacts the silicon cap layer to form a vertical interface that comprises:
an upper portion; and
a lower portion lower than the upper portion, wherein the lower portion laterally extends beyond the outer sidewall of the gate spacer more than the upper portion.