High-resolution FET VDS zero-volt-crossing timing detection scheme in a wireless power transfer system

1. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:

a comparator operable to receive the drain-to-source voltage of the transistor and compare it to a threshold voltage, the comparator comprising a clock input operable to receive a gate voltage of the transistor, wherein said received gate voltage is used to latch a result of said comparison to an output of the comparator; and

control circuitry operable to receive said comparator output and to perform a control function with respect to the transistor based on the value of the comparator output.

2. The control module of claim 1 wherein the comparator comprises:

a first output configured to provide an on-late flag indicative of whether the gate voltage turned the transistor on before or after the drain-to-source voltage went from high to low, wherein a rising edge of said received gate voltage is used to latch a result of said comparison to said first output of the comparator; and

a second output configured to provide an off-late flag indicative of whether the gate voltage turned the transistor off before or after the drain-to-source voltage went from low to high, wherein a falling edge of said received gate voltage is used to latch a result of said comparison to said second output of the comparator.

3. The control module of claim 2 wherein the control circuitry is operable to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

4. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the gate driver signal based on the value of the off-late flag.

5. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the PWM signal based on the value of the off-late flag.

6. The control module of claim 5 wherein the control circuitry is operable to average the value of the on-late flag over a plurality of PWM cycles and to average the value of the off-late flag over a plurality of PWM cycles, and to adjust the timing of the rising edge of the PWM signal based on the average value of the on-late flag and to adjust the timing of the falling edge of the PWM signal based on the average value of the off-late flag.

7. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:

a drain-to-source voltage comparator operable to receive the drain-to-source voltage (V ds ) of the transistor and compare it to a V ds threshold, the V ds comparator having at least one output configured to provide a V ds edge transition signal indicative of V ds crossing the V ds threshold;

a gate-to-source voltage comparator operable to receive the gate-to-source voltage (V gs ) of the transistor and compare it to a V gs threshold, the V gs comparator having at least one output configured to provide a V gs edge transition signal indicative of V gs crossing the V gs threshold;

at least one latching element having a data input, a clock input, and an output, the data input operably coupled to receive a V ds edge transition signal from the V ds comparator and the clock input operably coupled to receive a V gs edge transition signal from the V gs comparator such that the V gs edge transition signal serves to latch the V ds edge transition signal to the latch output.

8. The control module of claim 7 further comprising a delay-matching module operably coupled to receive the V ds edge transition signal from the V ds comparator and the V gs edge transition signal from the V gs comparator, apply a matching delay to at least one of the V ds edge transition signal and the V gs edge transition signal to compensate for any disparity in delays inherent in the V ds comparator and the V gs comparator, and to provide a delay-adjusted V ds edge transition signal to the data input of the at least one latching element and a delay-adjusted V gs edge transition signal to the clock input of the at least one latching element.

9. The control module of claim 7 further comprising control circuitry operable to receive the output of the at least one latching element and to perform a control function with respect to the transistor based on the value of said output of the at least one latching element.

10. The control module of claim 7 wherein the at least one latching element comprises at least one D flip-flop.

11. The control module of claim 7 wherein:

the V ds comparator comprises first and second outputs, the first output configured to provide a V ds rising-edge signal indicative of V ds rising above the V ds threshold, the second output configured to provide a V ds falling-edge signal indicative of V ds falling below the V ds threshold; and

the V gs comparator comprises first and second outputs, the first output configured to provide a V gs rising-edge signal indicative of V gs rising above the V gs threshold, the second output configured to provide a V gs falling-edge signal indicative of V gs falling below the V gs threshold.

12. The control module of claim 11 wherein the at least one latching element comprises:

a first latching element having a data input, a clock input, and an output, the data input operably coupled to receive the V ds falling-edge signal from the V ds comparator and the clock input operably coupled to receive the V gs rising-edge signal from the V gs comparator such that the V gs rising-edge signal serves to latch the V ds falling-edge signal to the latch output, the latch output thus serving as an on-late flag indicative of whether the V gs signal turned the transistor on before or after the drain-to-source voltage went from high to low; and

a second latching element having a data input, a clock input, and an output, the data input operably coupled to receive the V ds rising-edge signal from the V ds comparator and the clock input operably coupled to receive the V gs falling-edge signal from the V gs comparator such that the V gs falling-edge signal serves to latch the V ds rising-edge signal to the latch output, the latch output thus serving as an off-late flag indicative of whether the V gs signal turned the transistor off before or after the drain-to-source voltage went from low to high.

13. The control module of claim 12 further comprising control circuitry operable to receive the on-late flag and the off-late flag and to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

14. The control module of claim 12 further comprising:

a first delay-matching element operable to apply a matching delay to the V ds rising-edge signal to compensate for any disparity in delays inherent in the V ds comparator and the V gs comparator, and to provide a delay-adjusted V ds rising-edge signal to the data input of the second latching element;

a second delay-matching element operable to apply a matching delay to the V ds falling-edge signal to compensate for any disparity in delays inherent in the V ds comparator and the V gs comparator, and to provide a delay-adjusted V ds falling-edge signal to the data input of the first latching element;

a third delay-matching element operable to apply a matching delay to the V ds falling-edge signal to compensate for any disparity in delays inherent in the V ds comparator and the V gs comparator, and to provide a delay-adjusted V gs falling-edge signal to the clock input of the second latching element; and

a fourth delay-matching element operable to apply a matching delay to the V gs rising-edge signal to compensate for any disparity in delays inherent in the V ds comparator and the V gs comparator, and to provide a delay-adjusted V gs rising-edge signal to the clock input of the first latching element.

15. A method of controlling a field-effect transistor, comprising:

comparing, with a comparator, a drain-to source voltage of the transistor to a threshold voltage;

providing a gate voltage signal of the transistor to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator; and

performing a control function with respect to the transistor based on the value of the comparator output.

16. The method of claim 15 further comprising:

providing, at a first output of the comparator, an on-late flag indicative of whether the gate voltage signal turned the transistor on before or after the drain-to-source voltage went from high to low;

providing, at a second output of the comparator, an off-late flag indicative of whether the gate voltage signal turned the transistor off before or after the drain-to-source voltage went from low to high;

latching a result of said comparison to said first output of the comparator in response to receiving a rising edge of the gate voltage signal at said clock input; and

latching a result of said comparison to said second output of the comparator in response to receiving a falling edge of the gate voltage signal at said clock input.

17. The method of claim 16 wherein said performing a control function comprises performing at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

18. The method of claim 17 wherein said performing a control function comprises adjusting the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the gate driver signal based on the value of the off-late flag.

19. The method of claim 18 wherein said performing a control function comprises adjusting the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the PWM signal based on the value of the off-late flag.

20. The method of claim 19 wherein said performing a control function comprises averaging the value of the on-late flag over a plurality of PWM cycles, averaging the value of the off-late flag over a plurality of PWM cycles, adjusting the timing of the rising edge of the PWM signal based on the average value of the on-late flag, and adjusting the timing of the falling edge of the PWM signal based on the average value of the off-late flag.