Adaptive zero voltage switching for near field communication
Systems and methods for operating a wireless power transfer device are described. A circuit can generate a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground. The circuit can delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit can merge the first signal and the second signal to generate a third signal. A controller can use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. The first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.
1 . A semiconductor device comprising:
a controller;
a switching converter including a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor and a second LS transistor; and
a circuit configured to:
generate a first signal that indicates a voltage at a node between the first HS transistor and the first LS transistor falling below ground;
delay a gate-source voltage of the second LS transistor to generate a second signal; and
merge the first signal and the second signal to generate a third signal,
wherein the controller is configured to use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein the first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.
2 . The semiconductor device of claim 1 , wherein the switching converter is in a listener of a near field communication (NFC) power transfer system.
3 . The semiconductor device of claim 1 , wherein the circuit is configured to:
delay a gate-source voltage of the first LS transistor to generate a fourth signal;
generate a delay signal based on an arbitration between the first signal and the fourth signal; and
use the delay signal to adjust the delay being applied to the gate-source voltage of the second LS transistor, wherein adjustment to the delay adjusts the specific time.
4 . The semiconductor device of claim 3 , wherein the delay being applied to the gate-source voltage of the first LS transistor is a fixed delay.
5 . The semiconductor device of claim 3 , wherein:
in response to the arbitration indicating the first signal arrives at an arbiter before the fourth signal, generate the delay signal to decrease the delay; and
in response to the arbitration indicating the fourth signal arrives at the arbiter before the first signal, generate the delay signal to increase the delay.
6 . The semiconductor device of claim 1 , wherein the delay being applied to the gate-source voltage of the second LS transistor is a programmable delay.
7 . The semiconductor device of claim 1 , wherein a rising edge of a gate-source voltage of the first LS transistor aligns with a rising edge of the first signal at the specific time.
8 . A semiconductor device comprising:
a comparator configured to generate a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground;
a delay circuit configured to delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal; and
an OR gate configured to:
merge the first signal and the second signal to generate a third signal; and
send the third signal to a controller to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein the first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.
9 . The semiconductor device of claim 8 , wherein the switching converter is in a listener of a near field communication (NFC) power transfer system.
10 . The semiconductor device of claim 8 , wherein the delay circuit is a first delay circuit, and the semiconductor device further comprises:
a second delay circuit configured to delay a gate-source voltage of the first LS transistor to generate a fourth signal;
an arbiter configured to arbitrate between the first signal and the fourth signal; and
a counter configured to:
generate a delay signal based on the arbitration between the first signal and the fourth signal; and
send the delay signal to the controller to adjust the delay being applied to the gate-source voltage of the second LS transistor, wherein adjustment to the delay adjusts the specific time.
11 . The semiconductor device of claim 10 , wherein the delay being applied to the gate-source voltage of the first LS transistor is a fixed delay.
12 . The semiconductor device of claim 11 , wherein the fixed delay is equivalent to a propagation delay of the comparator.
13 . The semiconductor device of claim 10 , wherein the counter is configured to:
in response to the arbitration indicating the first signal arrives at an arbiter before the fourth signal, generate the delay signal to decrease the delay; and
in response to the arbitration indicating the fourth signal arrives at the arbiter before the first signal, generate the delay signal to increase the delay.
14 . The semiconductor device of claim 8 , wherein the delay being applied to the gate-source voltage of the second LS transistor is a programmable delay.
15 . The semiconductor device of claim 8 , wherein a rising edge of a gate-source voltage of the first LS transistor aligns with a rising edge of the first signal at the specific time.
16 . A method for operating a wireless power transfer device, the method comprising:
generating a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground;
delaying a gate-source voltage of a second LS transistor in the switching converter to generate a second signal;
merging the first signal and the second signal to generate a third signal; and
using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein the first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.
17 . The method of claim 16 , wherein the switching converter is in a listener of a near field communication (NFC) power transfer system.
18 . The method of claim 16 , further comprising:
delaying a gate-source voltage of the first LS transistor to generate a fourth signal;
generating a delay signal based on an arbitration between the first signal and the fourth signal; and
using the delay signal to adjust the delay being applied to the gate-source voltage of the second LS transistor, wherein adjustment to the delay adjusts the specific time.
19 . The method of claim 18 , wherein:
in response to the arbitration indicating the first signal arrives at an arbiter before the fourth signal, generating the delay signal to decrease the delay; and
in response to the arbitration indicating the fourth signal arrives at the arbiter before the first signal, generating the delay signal to increase the delay.
20 . The method of claim 18 , wherein a rising edge of a gate-source voltage of the first LS transistor aligns with a rising edge of the first signal at the specific time.