Resistive memory arrays for performing multiply-accumulate operations

1. A resistive memory array comprising:

a number of resistive memory elements to receive a common-valued read signal, in which a resistance of a resistive memory element defines a value within a matrix;

a number of multiplication engines to perform a multiply operation by:

receiving a memory element output from a corresponding resistive memory element;

receiving an input signal; and

generating a multiplication output based on a received memory element output and a received input signal;

a conditioning resistor to condition the multiplication outputs; and

an accumulation engine to sum the multiplication outputs from the number of multiplication engines, in which the summed multiplication outputs represent a multiplication of the matrix and a number of input signals.

2. The array of claim 1 , in which the number of resistive memory elements are to receive one of a shared read signal and distinct instances of read signals having the same value.

3. The array of claim 1 , in which the number of multiplication engines comprise a voltage-to-resistance converter to convert an input voltage signal into an input resistance.

4. The array of claim 1 , in which the number of multiplication engines comprise a current-to-resistance converter to convert an input current signal into an input resistance.

5. The array of claim 1 , in which the number of resistive memory elements are memristors.

6. The array of claim 1 , in which each of the number of multiplication engines is respectively coupled to a corresponding one of the number of resistive memory elements.

7. A method for performing a multiply-accumulate operation, the method comprising:

applying a common-valued read signal to inputs of a number of resistive memory elements;

applying a number of input signals to a number of multiplication engines, in which a multiplication engine is coupled to a resistive memory element;

conditioning a number of the multiplication outputs;

summing a number of the multiplication outputs from the number of multiplication engines, in which a multiplication output represents a multiplication of a resistive memory element output and an input signal; and

determining an array output based on a summed number of the multiplication outputs.

8. The method of claim 7 , in which:

the common-valued read signal comprises a common-valued read voltage;

the resistive memory element output comprises a current;

the number of input signals comprises a number of input voltages;

the number of multiplication outputs comprise a number of multiplication output voltages; and

the array output comprises an array output voltage.

9. The method of claim 7 , in which conditioning the number of multiplication outputs comprises passing the number of multiplication outputs through a conditioning resistor, in which a multiplication engine is coupled to a corresponding conditioning resistor.

10. The method of claim 7 , in which:

applying a number of input signals to a number of multiplication engines comprises applying a vector input signal to the number of multiplication engines; and

an entry in the vector input signal is directed to a different multiplication engine.

11. The method of claim 7 , in which applying a common-valued read signal to inputs of a number of resistive memory elements comprises applying a common-valued read voltage that is a largest voltage less than a switching voltage of the number of resistive memory elements.

12. A computing device comprising:

a processor; and

a resistive memory array coupled to the processor, the resistive memory array comprising:

a number of resistive memory elements to receive a common-valued read voltage, in which a resistance of a resistive memory element defines a value within a matrix;

a number of multiplication engines to perform a multiplication operation, in which each multiplication engine:

is respectively coupled to a resistive memory element;

is to receive a resistive memory element output current;

is to output a multiplication current;

comprises an operational amplifier to amplify the resistive memory element output current; and

comprises an input converter to convert a received input voltage into a resistance, in which the received input voltage represents an input signal to be multiplied by the matrix;

a conditioning resistor to condition a number of the output multiplication currents; and

an accumulation engine to sum a number of the multiplication currents to generate an array output voltage.

13. The computing device of claim 12 , in which the resistive memory array is a resistive crossbar array comprising:

a number of row lines; and

a number of column lines intersecting the row lines to form a number of junctions;

in which the number of resistive memory elements are coupled between the row lines and the column lines at the junctions.

14. The computing device of claim 12 , in which the voltage-to-resistance converter is a metal-oxide semiconductor field-effect transistor (MOSFET).