Granted Patent B2

US 12,387,090 · App. 17/560,801 · Granted Aug 12, 2025

Inventors: Xinyi Li (Beijing, CN); Huaqiang Wu (Beijing, CN); He Qian (Beijing, CN); Dong Wu (Beijing, CN)

Assignee: TSINGHUA UNIVERSITY

G06N3/063G06N3/04

Abstract

Claims (40)

1. A neuron simulation circuit, comprising: an operational amplifier, a first resistive device, and a second resistive device,

wherein the operational amplifier comprises a first input terminal, a second input terminal, and an output terminal, and the first resistive device is connected between the first input terminal or the second input terminal of the operational amplifier and the output terminal of the operational amplifier;

the second resistive device is connected between the output terminal of the operational amplifier and an output terminal of the neuron simulation circuit;

the second resistive device comprises a threshold switching memristor, and a first terminal of the threshold switching memristor is electrically connected with the output terminal of the neuron simulation circuit; and

at least one selected from the group consisting of the first resistive device and the second resistive device comprises a dynamic memristor.

2. The neuron simulation circuit of claim 1 , wherein the first resistive device comprises the dynamic memristor,

a first terminal of the dynamic memristor is electrically connected with the first input terminal or the second input terminal of the operational amplifier, and a second terminal of the dynamic memristor is electrically connected with the output terminal of the operational amplifier.

3. The neuron simulation circuit of claim 2 , further comprising a resistor,

wherein a first terminal of the resistor is electrically connected with the output terminal of the neuron simulation circuit and a second terminal of the resistor is electrically connected with a first voltage terminal.

4. The neuron simulation circuit of claim 1 , further comprising a resistor,

wherein a first terminal of the resistor is electrically connected with the output terminal of the neuron simulation circuit and a second terminal of the resistor is electrically connected with a first voltage terminal.

5. The neuron simulation circuit of claim 1 , wherein the second resistive device comprises the dynamic memristor, and

the dynamic memristor is in series connection or in parallel connection with the threshold switching memristor.

6. The neuron simulation circuit of claim 5 , wherein the dynamic memristor is in series connection with the threshold switching memristor;

a first terminal of the dynamic memristor is electrically connected with the output terminal of the operational amplifier, and a second terminal of the dynamic memristor is electrically connected with a second terminal of the threshold switching memristor.

7. The neuron simulation circuit of claim 6 , wherein the first resistive device comprises a first resistor;

a first terminal of the first resistor is electrically connected with the first input terminal or the second input terminal of the operational amplifier, and a second terminal of the first resistor is electrically connected with the output terminal of the operational amplifier and the first terminal of the dynamic memristor.

8. The neuron simulation circuit of claim 7 , further comprising a second resistor,

wherein a first terminal of the second resistor is electrically connected with the output terminal of the neuron simulation circuit, and a second terminal of the second resistor is electrically connected with a first voltage terminal.

9. The neuron simulation circuit of claim 8 , wherein the first terminal of the first resistor is electrically connected with the first input terminal of the operational amplifier, and the second input terminal of the operational amplifier and the first voltage terminal are both grounded.

10. The neuron simulation circuit of claim 9 , wherein the first input terminal of the operational amplifier is a non-inverting input terminal.

11. The neuron simulation circuit of claim 5 , wherein the dynamic memristor is in parallel connection with the threshold switching memristor, and a first terminal of the dynamic memristor is electrically connected with the first terminal of the threshold switching memristor; and

a second terminal of the dynamic memristor is electrically connected with a second terminal of the threshold switching memristor, and is electrically connected with the output terminal of the operational amplifier.

12. The neuron simulation circuit of claim 11 , wherein the first resistive device comprises a first resistor;

a first terminal of the first resistor is electrically connected with the first input terminal or the second input terminal of the operational amplifier, and a second terminal of the first resistor is electrically connected with the output terminal of the operational amplifier, the first terminal of the dynamic memristor and the first terminal of the threshold switching memristor.

13. The neuron simulation circuit of claim 12 , further comprising a second resistor,

a first terminal of the second resistor is electrically connected with the output terminal of the neuron simulation circuit, and a second terminal of the second resistor is electrically connected with a first voltage terminal.

14. The neuron simulation circuit of claim 13 , wherein the first terminal of the first resistor is electrically connected with the first input terminal of the operational amplifier, and the second input terminal of the operational amplifier and the first voltage terminal are both grounded.

15. The neuron simulation circuit of claim 14 , wherein the first input terminal of the operational amplifier is a non-inverting input terminal.

16. The neuron simulation circuit of claim 1 , wherein the first resistive device comprises a first dynamic memristor,

a first terminal of the first dynamic memristor is electrically connected with the first input terminal or the second input terminal of the operational amplifier, and a second terminal of the first dynamic memristor is electrically connected with the output terminal of the operational amplifier; and

the second resistive device comprises a second dynamic memristor in series connection or in parallel connection with the threshold switching memristor.

17. The neuron simulation circuit of claim 16 , further comprising a resistor,

a first terminal of the resistor is electrically connected with the output terminal of the neuron simulation circuit, and a second terminal of the resistor is electrically connected with a first voltage terminal.

18. The neuron simulation circuit of claim 17 , wherein the first terminal of the first dynamic memristor is electrically connected with the first input terminal of the operational amplifier, and the second input terminal of the operational amplifier and the first voltage terminal are both grounded.

19. A neural network apparatus, comprising at least one neuron unit,

wherein the at least one neuron unit comprises the neuron simulation circuit of claim 1 .

20. The neural network apparatus of claim 19 , further comprising a synapse array simulation circuit,

wherein an output signal of the synapse array simulation circuit is provided to the first input terminal or the second input terminal, which is connected with the first resistive device, of the operational amplifier of the at least one neuron unit; and

the synapse array simulation circuit comprises a plurality of non-volatile memristors arranged in an array.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (12)