IP Library › Granted Patent US 10,026,474
Granted Patent B2
US 10,026,474 · App. 15/116,105 · Granted Jul 17, 2018

Switched memristor analog tuning

Inventor: Brent Buchanan (Palo Alto, CA)
Assignee: Hewlett Packard Enterprise Development LP
G11C13/0021G11C13/0007H01L27/2436H01L27/2463H01L45/08H01L45/1233H01L45/142H01L45/144H01L45/145H01L45/146H01L45/147G11C2213/31G11C2213/32G11C2213/34G11C2213/79
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Quick Facts
Patent No.
US 10,026,474
App. No.
15/116,105
Granted
Jul 17, 2018
Kind
B2
Abstract

Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.

Claims (25)

1. A switched memristor tuned analog apparatus, comprising:

a plurality of switched memristors connected in series to provide a switch-selectable programmed resistance, a switched memristor of the plurality comprising a memristor connected in parallel with a switch, the switch to select the memristor, the memristor having a programmable analog resistance to provide a programmed resistance of the switch-selectable programmed resistance;

a resistance-tunable analog circuit connected to the plurality of switched memristors, the switch-selectable programmed resistance of the plurality of switched memristors to provide rapid memristor-based tuning of an analog attribute of the resistance-tunable analog circuit; and

another switched memristor connected in series with the plurality of switched memristors, the other switched memristor to serve as a spare in event of a failure of a switched memristor of the plurality of switched memristors.

2. The switched memristor tuned analog apparatus of claim 1 , wherein the switch of the switched memristor comprises a field effect transistor (FET) with a source of the FET connected to a first terminal of the memristor and a drain of the FET connected to a second terminal of the memristor.

3. The switched memristor tuned analog apparatus of claim 1 , wherein the switch-selectable programmed resistance is to be changed to tune the resistance-tunable analog circuit one or both of by programming the programmable analog resistance of the memristor and by activating the switch of the switched memristor.

4. The switched memristor tuned analog apparatus of claim 1 , wherein the resistance-tunable analog circuit comprises an analog filter, the analog attribute being a frequency characteristic of the analog filter determined by the switch-selectable programmed resistance.

5. The switched memristor tuned analog apparatus of claim 4 , wherein the analog filter comprises a capacitor connected to the plurality of switched memristors.

6. The switched memristor tuned analog apparatus of claim 1 , wherein the resistance-tunable analog circuit comprises an oscillator, a frequency of the oscillator to be determined by the switch-selectable programmed resistance.

7. The switched memristor tuned analog apparatus of claim 1 , wherein the resistance-tunable analog circuit comprises an amplifier, a gain of the amplifier to be determined by the switch-selectable programmed resistance.

8. A switched memristor analog system comprising:

a switched memristor array comprising a plurality of switch selectable memristors, the switched memristor array to provide a switch-selectable programmable resistance;

a resistance-tunable analog circuit, the switch-selectable programmable resistance of the switched memristor array to provide rapid memristor-based tuning of an analog attribute of the resistance-tunable analog circuit;

a switch controller to provide selection of one or more of the switch selectable memristors of the switched memristor array,

wherein the switch-selectable programmable resistance is provided by both switch selection of a switch selectable memristor of the array and a programmable resistance of the selected switch selectable memristor; and

another switch selectable memristor connected to the switched memristor array, the other switch selectable memristor to serve as a spare in event of a failure of the switch selectable memristor of the switched memristor array.

9. The switched memristor analog system of claim 8 , wherein the switch selectable memristors of the array are connected in series, the switch selectable memristor comprising a field effect transistor (FET) connected in parallel with a memristor with a source of the FET being connected to a first terminal of the memristor and a drain of the FET being connected to a second terminal of the memristor.

10. The switched memristor analog system of claim 8 , wherein the resistance-tunable analog circuit comprises one or more of an analog filter, an amplifier, and an oscillator.

11. A method of analog tuning using a switched memristor array, the method comprising:

programming a memristor of a switched memristor array;

activating a switch of the switched memristor array to select the programmed memristor and to establish an analog resistance of the switched memristor array;

providing rapid memristor-based tuning of a resistance-tunable analog circuit using the established analog resistance; and

providing another switch selectable memristor connected to the switched memristor array, the other switch selectable memristor to serve as a spare in event of a failure of the switch selectable memristor of the switched memristor array.

12. The method of analog tuning of claim 11 , wherein a switched memristor of the switched memristor array comprises a switch connected in parallel with the memristor, the switch comprising a field effect transistor (FET).

13. The method of analog apparatus tuning of claim 11 , wherein the resistance-tunable analog circuit comprises one or more of an analog filter, an amplifier, an attenuator and an oscillator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2016
From: BUCHANAN, BRENT
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 040394/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2016
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 040660/0075 →
Continuity (1)
Related Publication 20170148513A1 · May 25, 2017
Cited By (1)
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