Circuit arrangement for a safety IandC system
A circuit arrangement, in particular for a safety I&C system of a nuclear power plant, keeps a proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement includes: a generic FPGA with a plurality of logic blocks, and at least one dedicated PLD which operates as an application-specific switch-matrix for the logic blocks.
1. A circuit arrangement disposed on a logic board, the circuit arrangement comprising:
an FPGA including a plurality of logic function units each having inputs and outputs, a set of internal routing resources for interconnections between said inputs and outputs of said logic function units, and a plurality of pins;
at least one application specific PLD having a plurality of pins; and
circuit tracks disposed on the logic board and providing a plurality of connections between said pins of said FGPA and said pins of said PLD;
said internal routing resources of said FPGA not interconnecting said inputs of said logic function units of said FGPA and said outputs of said logic function units of said FGPA; and
said at least one PLD operating as an application-specific, switch-matrix for said connections and for said inputs of said logic function units of said FGPA and said outputs of said logic function units of said FGPA, said switch-matrix located externally from said FGPA.
2. The circuit arrangement according to claim 1 , wherein said at least one PLD provides a range of functions being mainly or exclusively restricted to a switch-matrix for said FPGA.
3. The circuit arrangement according to claim 1 , wherein said switch-matrix for said logic function units of said FPGA is exclusively provided by said at least one PLD.
4. The circuit arrangement according to claim 1 , wherein said FPGA and said at least one PLD are disposed on a common circuit board and pin-wise connected to each other by circuit-tracks.
5. The circuit arrangement according to claim 1 , wherein said at least one PLD is precisely one PLD dedicated to said FPGA.
6. The circuit arrangement according to claim 5 , wherein said one PLD is a CPLD.
7. The circuit arrangement according to claim 5 , wherein said one PLD is a FPGA.
8. The circuit arrangement according to claim 5 , wherein said one PLD is an ASIC.
9. The circuit arrangement according to claim 5 , wherein said one PLD is disposed on a PCB.
10. The circuit arrangement according to claim 1 , wherein said plurality of connections is at least 50.
11. The circuit arrangement according to claim 1 , wherein said plurality of connections is greater than 200.
12. A safety I&C system of a nuclear power plant, the safety I&C system comprising at least one circuit arrangement according to claim 1 .
13. The circuit arrangement according to claim 1 , further comprising a Non-Volatile Memory module containing a pre-defined switch configuration which is loaded into said at least one PLD during power-up or setup.
14. The circuit arrangement according to claim 1 , further comprising a Non-Volatile Memory module having pre-defined logic definitions to be loaded into said FPGA during power-up.
15. The circuit arrangement according to claim 1 , further comprising a Non-Volatile Memory module having a set of reference/parameter values to be loaded into said FPGA during power-up.
16. The circuit arrangement according to claim 1 , wherein said NVMs are physically combinable.
17. The circuit arrangement according to claim 1 , further comprising an auxiliary module having at least one helper function for performing a function selected from the group consisting of PLD configuration, integrity checks, and power supply monitoring.
18. The circuit arrangement according to claim 1 , further comprising an auxiliary module having at least one helper function for performing a function selected from the group consisting of PLD configuration, integrity checks, and power supply monitoring including monitoring a local power supply of a daughter board.
19. The circuit arrangement according to claim 1 , further comprising at least one helper function for performing a function selected from the group consisting of PLD configuration, integrity checks, and power supply monitoring including monitoring a local power supply of a daughter board, wherein said at least one helper function is at least partially implemented within said at least one PLD.
20. The circuit arrangement according to claim 1 , wherein said switch-matrix interconnects said logic function units of said FGPA together.