System and method for multi-cycle write leveling
A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.
1. A method for synchronizing a clock signal with a data strobe signal, said method comprising the following steps:
performing a first write operation on a memory module and writing a first data pattern onto a first memory location of the memory module;
performing a second write operation on the memory module, and writing a second data pattern onto a second memory location of the memory module;
performing a third write operation on the memory module, and writing a third data pattern onto a third memory location of the memory module;
iteratively masking at least two beats of the data strobe signal corresponding to said first write operation;
iteratively masking at least six beats of the data strobe signal corresponding to said second write operation;
determining a target pattern to be read from the memory module, based at least on gated data strobe signals;
performing a data read operation on said memory module and reading data stored thereupon, and forming a forth data pattern, said forth data pattern comprising the data read from said memory module;
determining whether said forth data pattern is equivalent to the target data pattern;
determining cycle delay between the clock signal and the data strobe signal corresponding to the data read operation, only in the event that the forth data pattern is determined to be not equivalent to the target data pattern;
selectively calibrating the data strobe signal and corresponding data signal with the clock signal by delaying the data strobe signal and corresponding data signal based on said cycle delay;
determining a burst length, said burst length having a value equivalent to number of beats that can be written into and read from said memory module, in one write operation and one read operation respectively; and
configuring said first data pattern, second data pattern and third data pattern to incorporate the number of beats equivalent to the value specified by the burst length.
2. The method as claimed in claim 1 , wherein said first memory location, second memory location and third memory location are consecutive memory locations.
3. The method as claimed in claim 1 , wherein the step of performing a data read operation on said memory module, further includes the step of initiating said data read operation from said second memory location of said memory module.
4. The method as claimed in claim 1 , wherein the forth data pattern is a combination of at least parts of said first data pattern and second data pattern written into said memory module via said first write operation and second write operation.
5. The method as claimed in claim 1 , wherein the step of delaying said data strobe signal and corresponding data signal, further includes the step of delaying the data strobe signal and corresponding data signal based on said cycle delay for every repetition of a sequence of a write operation and a read operation.
6. A system for synchronizing a clock signal with a data strobe signal, said system comprising at least one memory module cooperating with a memory controller, wherein said memory controller is configured to:
perform a first write operation on the memory module, and write a first data pattern thereto;
perform a second write operation on the memory module, and write a second data pattern thereto;
perform a third write operation on the memory module, and write a third pattern thereto;
iteratively mask at least two beats of data strobe signal corresponding to said first write operation;
iteratively mask at least six beats of the data strobe signal corresponding to said second write operation;
determine a target pattern to be read from the memory module, based at least on gated data strobe signals;
perform a data read operation on said memory module and read data stored thereupon, and generate a forth data pattern incorporating the data read from said memory module;
determine whether said forth data pattern is equivalent to the target data pattern;
determine a cycle delay between the clock signal and the data strobe signal corresponding to the data read operation, only in the event that the firth data pattern is determined not to be equivalent to the target data pattern;
selectively calibrate the data strobe signal and corresponding data signal with the clock signal by delaying the data strobe signal and corresponding data signal based on said cycle delay;
determine a burst length, said burst length having a value equivalent to number of beats that can be written into and read from said memory module, in one write operation and one read operation respectively; and
configure said first data pattern, second data pattern and third data pattern to incorporate the number of beats equivalent to the value specified by the burst length.