IP Library › Granted Patent US 10,049,748
Granted Patent B2
US 10,049,748 · App. 15/582,103 · Granted Aug 14, 2018

Semiconductor memory device and method for program operation having program loops by step voltage

Inventors: Yong Hwan Hong (Gyeonggi-do, KR); Byung Ryul Kim (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
G11C16/12
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Quick Facts
Patent No.
US 10,049,748
App. No.
15/582,103
Granted
Aug 14, 2018
Kind
B2
Abstract

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.

Claims (166)

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells;

a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells; and

a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop,

wherein the control circuit comprises a program voltage control unit configured to update the step voltage according to Equation 1 at a start of each step interval defined by Equation 2 given a total of 2 N steps corresponding to the preset time period as follows:

Vstep

⁡

(

n

)

=

(

VPGM_TARGET

-

VCURRENT

)

REMAINING

⁢

⁢

STEPS

,

[

Equation

⁢

⁢

1

]

where “VPGM TARGET” represents the target program voltage, “VCURRENT” represents a current program voltage of the selected word line, “REMAINING STEPS” represents a number of remaining steps in the total steps at the start of each step interval, and “n” is a natural number ranging from 1 to N+1; and

n

th

⁢

⁢

step

⁢

⁢

interval

⁢

⁢

(

unit

⁢

:

⁢

⁢

step

)

=

{

2

N

+

1

-

n

-

2

N

-

n

n

=

1

N

1

n

=

N

+

1

,

[

Equation

⁢

⁢

2

]

where “n” is a natural number ranging from 1 to N+1.

2. The semiconductor memory device according to claim 1 , wherein the program voltage control unit comprises:

a step counter circuit configured to count the number of remaining steps as the program voltage is applied to the selected word line; and

a step voltage calculation unit configured to update the step voltage according to the equation 1.

3. The semiconductor memory device according to claim 1 , wherein the preset time period is equally applied to the plurality of program loops.

4. The semiconductor memory device according to claim 1 , wherein each of the total steps has a length corresponding to one of one period and a half period of a clock signal of the semiconductor memory device.

5. A method for operating a semiconductor memory device, comprising:

applying a pass voltage to all word lines;

when a voltage of the word lines reaches the pass voltage, applying a program start voltage higher than the pass voltage to a selected word line among the word lines; and

when the voltage of the selected word line reaches the program start voltage, applying a program voltage to the selected word line during a preset time period of each of a plurality of program loops,

wherein the program voltage is stepwisely increased from the program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during the preset time period, and

wherein the applying the program voltage comprises updating the step voltage according to Equation 1 at a start of each step interval defined by Equation 2 given a total of 2 N steps corresponding to the preset time period as follows:

Vstep

⁡

(

n

)

=

(

VPGM_TARGET

-

VCURRENT

)

REMAINING

⁢

⁢

STEPS

,

[

Equation

⁢

⁢

1

]

where “VPGM TARGET” represents the target program voltage, “VCURRENT” represents a current program voltage of the selected word line, “REMAINING STEPS” represents a number of remaining steps in the total steps at the start of each step interval, and “n” is a natural number ranging from 1 to N+1; and

n

th

⁢

⁢

step

⁢

⁢

interval

⁢

⁢

(

unit

⁢

:

⁢

⁢

step

)

=

{

2

N

+

1

-

n

-

2

N

-

n

n

=

1

N

1

n

=

N

+

1

,

[

Equation

⁢

⁢

2

]

where “n” is a natural number ranging from 1 to N+1.

6. The method according to claim 5 , wherein the preset time is equally applied to the plurality of program loops.

7. The method according to claim 5 , wherein each of the total steps has a length corresponding to one of one period and a half period of a clock signal of the semiconductor memory device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2017
From: HONG, YONG HWAN; KIM, BYUNG RYUL
To: SK HYNIX INC.
Reel/Frame 042372/0443 →
Priority Claims (1)
KR 10-2016-0122219 · Sep 23, 2016 · national
Continuity (1)
Related Publication 20180090209A1 · Mar 29, 2018
Cited By (1)
US 12,725,642