Granted Patent B2

US 12,725,642 · App. 18/809,451 · Granted Sep 1, 2026

Inventors: Kuan-Chih Chen (New Taipei City, TW); Ming-Hsiu Lee (Hsinchu City, TW)

Assignee: MACRONIX INTERNATIONAL CO., LTD.

G11C7/1078G11C5/145

Abstract

Claims (63)

1 . A memory device, comprising:

a memory array, comprising a first array and a second array;

a voltage generator, coupled to the memory array; and

an array control circuit, coupled to the memory array and the voltage generator, and configured to:

in a programming stage of the memory array:

control the voltage generator to generate a first control voltage to the memory array; and

generate a temporary address to control the first array to store a storage data and an address data in a first programming step according to the temporary address and the first control voltage,

in an idle stage of the memory array:

control the voltage generator to generate a second control voltage to the memory array;

controlling the second array to store the storage data in a second programming step according to the address data and the second control voltage; and

control the first array to perform an erasing operation,

wherein a voltage value of the first programming step is greater than a voltage value of the second programming step.

2 . The memory device of claim 1 , further comprising an input circuit, wherein the input circuit is coupled to the memory array and the array control circuit, and is configured to split an input data into the storage data and the address data.

3 . The memory device of claim 1 , further comprising a sensing/adjusting circuit, wherein the sensing/adjusting circuit is coupled to the voltage generator and the array control circuit, and is configured to adjust the voltage value of the first programming step and the voltage value of the second programming step according to at least one adjustment parameter in the programming stage and the idle stage.

4 . The memory device of claim 1 , wherein the memory array is configured to generate a plurality of first output voltages based on the first control voltage, the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-count graph, and

wherein the memory array is configured to generate a plurality of second output voltages based on the second control voltage, the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-count graph.

5 . The memory device of claim 4 , wherein the spacing between adjacent two of the plurality of first subsets is negatively related to the voltage value of the first programming step, and the spacing between adjacent two of the plurality of second subsets is negatively related to the voltage value of the second programming step.

6 . The memory device of claim 1 , wherein the memory array is divided into a plurality of sub-blocks by a plurality of word lines, one of the plurality of sub-blocks is at least partially configured as the first array, and the remaining at least one of the plurality of sub-blocks is configured as the second array.

7 . The memory device of claim 1 , wherein the memory array is divided into a plurality of sub-blocks by a plurality of word lines, a first block of each of the plurality of sub-blocks is configured as the first array, and a second block of each of the plurality of sub-blocks is configured as the second array.

8 . The memory device of claim 1 , wherein the voltage value of the first programming step is between 1 volt and 3 volts.

9 . An operation method, suitable for a memory device, comprising:

receiving, by a memory array of the memory device, a storage data and an address data;

activating, by an array control circuit of the memory device, a voltage generator of the memory device, in a programming stage of the memory array, so as to generate a first control voltage to the memory array;

generating, by the array control circuit, a temporary address, in the programming stage, so as to control a first array of the memory array to store the storage data and the address data in a first programming step according to the temporary address and the first control voltage;

activating, by the array control circuit, the voltage generator, in an idle stage of the memory array, so as to generate a second control voltage to the memory array;

controlling, by the array control circuit, a second array of the memory array to store the storage data in a second programming step according to the address data and the second control voltage, in the idle stage; and

controlling, by the array control circuit, the first array to perform an erasing operation, in the idle stage,

wherein a voltage value of the first programming step is greater than a voltage value of the second programming step.

10 . The operation method of claim 9 , wherein receiving, by the memory array of the memory device, the storage data and the address data comprises:

receiving, by an input circuit of the memory device, an input data;

splitting, by the input circuit, the input data into the storage data and the address data; and

transmitting, by the input circuit, the storage data and the address data to the memory array.

11 . The operation method of claim 9 , further comprising:

adjusting, by a sensing/adjusting circuit of the memory device, the voltage value of the first programming step according to at least one adjustment parameter, in the programming stage; and

adjusting, by the sensing/adjusting circuit, the voltage value of the second programming step according to the at least one adjustment parameter, in the idle stage.

12 . The operation method of claim 9 , further comprising:

generating, by the memory array, a plurality of first output voltages based on the first control voltage, wherein the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-count graph; and

generating, by the memory array, a plurality of second output voltages based on the second control voltage, wherein the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-count graph.

13 . The operation method of claim 12 , wherein the spacing between adjacent two of the plurality of first subsets is negatively related to the voltage value of the first programming step, and the spacing between adjacent two of the plurality of second subsets is negatively related to the voltage value of the second programming step.

14 . The operation method of claim 9 , further comprising:

dividing, by a plurality of word lines of the memory device, the memory array into a plurality of sub-blocks;

configuring, by the array control circuit, one of the plurality of sub-blocks at least partially as the first array; and

configuring, by the array control circuit, the remaining at least one of the plurality of sub-blocks as the second array.

15 . The operation method of claim 9 , further comprising:

dividing, by a plurality of word lines of the memory device, the memory array into a plurality of sub-blocks;

configuring, by the array control circuit, a first block of each of the plurality of sub-blocks as the first array; and

configuring, by the array control circuit, a second block of each of the plurality of sub-blocks as the second array.

16 . The operation method of claim 9 , wherein the voltage value of the first programming step is between 1 volt and 3 volts.

17 . A memory system, comprising a plurality of memory devices, wherein each of the plurality of memory devices comprises:

a memory array;

a voltage generator, coupled to the memory array; and

an array control circuit, coupled to the memory array and the voltage generator,

wherein the memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array,

wherein in a programming stage of the memory system, the array control circuit of the at least one first memory device is configured to control the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and is configured to generate a temporary address to the first array to control the first array to store a storage data and an address data in a first programming step according to the temporary address and the first control voltage,

wherein in an idle stage of the memory system, the array control circuit of the at least one second memory device is configured to control the voltage generator of the at least one second memory device to generate a second control voltage to the second array, and is configured to control the second array to store the storage data in a second programming step according to the address data and the second control voltage, and the array control circuit of the at least one first memory device is configured to control the first array to perform an erasing operation,

wherein a voltage value of the first programming step is greater than a voltage value of the second programming step.

18 . The memory system of claim 17 , wherein each of the plurality of memory devices further comprises an input circuit,

wherein the input circuit is coupled to the memory array and the array control circuit, and is configured to split an input data into the storage data and the address data.

19 . The memory system of claim 17 , wherein each of the plurality of memory devices further comprises a sensing/adjusting circuit,

wherein the sensing/adjusting circuit is coupled to the voltage generator and the array control circuit, and is configured to adjust the voltage value of the first programming step and the voltage value of the second programming step according to at least one adjustment parameter in the programming stage and the idle stage.

20 . The memory system of claim 17 , wherein the memory array is configured to generate a plurality of first output voltages based on the first control voltage, the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-count graph,

wherein the memory array is configured to generate a plurality of second output voltages based on the second control voltage, the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-count graph, and

wherein the spacing between adjacent two of the plurality of first subsets is negatively related to the voltage value of the first programming step, and the spacing between adjacent two of the plurality of second subsets is negatively related to the voltage value of the second programming step.

Assignments (1)

Continuity (1)

References Cited (9)