Transient sensing of memory cells
The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.
1. A method for sensing a resistance state of a memory cell, which includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector coupled in series between first and second conductive lines, the method comprising the steps of:
precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector;
allowing a voltage of the first conductive line to decay by discharging through the second conductive line;
measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell;
concluding that the memory cell is in a high resistance state if the measured voltage is greater than a reference level; and
concluding that the memory cell is in a low resistance state if the measured voltage is less than the reference level,
wherein the discharge period is longer than or equal to a time period required for the two-terminal selector to turn off during discharging when the memory cell is in the high resistance state.
2. The method of claim 1 , wherein the first conductive line has a higher precharged potential than the second conductive line.
3. The method of claim 1 , wherein the step of precharging includes precharging the second conductive line.
4. The method of claim 3 , the first conductive line is precharged to a positive potential and the second conductive line is precharged to a negative potential.
5. The method of claim 1 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by grounding the second conductive line.
6. The method of claim 1 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by biasing the second conductive line to a negative potential.
7. The method of claim 1 , wherein the discharge period is longer than or equal to a time period required for the two-terminal selector to automatically turn off during discharging when the memory cell is in the low resistance state.
8. The method of claim 1 , wherein the discharge period is shorter than or equal to a time period required for the two-terminal selector to automatically turn off during discharging when the memory cell is in the low resistance state.
9. A method for sensing a resistance state of a memory cell, which includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector coupled in series between first and second conductive lines, the method comprising the steps of:
precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector;
allowing a voltage of the first conductive line to decay by discharging through the second conductive line; and
measuring the voltage of the first conductive line after a first discharge period and a second discharge period that is different from the first discharge period and determining a voltage difference between the first and second discharge periods to ascertain whether the memory cell is in a low resistance state or a high resistance state.
10. The method of claim 9 further comprising steps of:
concluding that the memory cell is in the low resistance state if an absolute value of the voltage difference is greater than a reference value; and
concluding that the memory cell is in the high resistance state if the absolute value of the voltage difference is less than the reference value.
11. The method of claim 9 , wherein the first conductive line has a higher precharged potential than the second conductive line.
12. The method of claim 9 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by grounding the second conductive line.
13. The method of claim 9 , wherein the step of allowing a voltage of the first conductive line to decay is accomplished by biasing the second conductive line to a negative potential.