Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.
1. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip,
wherein the first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole,
one surface of the first interconnection member in contact with the second interconnection member includes a first region surrounding the through-hole and a second region surrounding the first region,
the blocking layer of the first interconnection member is disposed in the first region,
the first redistribution layer of the first interconnection member is disposed in the second region,
the blocking layer is a plating layer disposed on the first insulating layer of the first interconnection member, and
the first redistribution layer of the first interconnection member is disposed on the same level as that of the blocking layer.
2. The fan-out semiconductor package of claim 1 , wherein the blocking layer continuously surrounds the through-hole.
3. The fan-out semiconductor package of claim 1 , wherein a side surface of the blocking layer is in contact with the encapsulant, and
a lower surface of the blocking layer is in contact with the second interconnection member.
4. The fan-out semiconductor package of claim 1 , wherein an interface between the blocking layer and the second interconnection member is disposed on a level different from that of at least one of an interface between the first redistribution layer and the second interconnection member and an interface between the first insulating layer and the second interconnection member.
5. The fan-out semiconductor package of claim 1 , wherein the plating layer has a thickness equal to or greater than that of the first redistribution layer of the first interconnection member.
6. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip,
wherein the first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer, which is a plating layer, disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole,
the first interconnection member further includes a second insulating layer, and a second redistribution layer and a third redistribution layer disposed on opposite surfaces of the second insulating layer, respectively, and
the first insulating layer is disposed on the second insulating layer and covers the second redistribution layer, and the first redistribution layer is disposed on the first insulating layer.
7. The fan-out semiconductor package of claim 6 , wherein the first interconnection member further includes a third insulating layer disposed on the second insulating layer and covering the third redistribution layer and a fourth redistribution layer disposed on the third insulating layer.
8. The fan-out semiconductor package of claim 6 , wherein the second insulating layer has a thickness greater than that of the first insulating layer.
9. The fan-out semiconductor package of claim 6 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.
10. The fan-out semiconductor package of claim 6 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.
11. The fan-out semiconductor package of claim 6 , wherein a lower surface of the first redistribution layer is disposed on a level below a lower surface of the connection pad.