Magnetic random access memory with dynamic random access memory (DRAM)-like interface
View Patent ↗A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
1. A memory device configured to emulate dynamic random access memory (DRAM) comprising:
a memory array including a plurality of memory cells organized into rows and columns, at least one row of memory cells comprising one or more pages that store data during a burst write operation, said data including sequential data units that are written to a page;
a control circuit operable to:
initiate said burst write operation that writes said data to said memory array, said burst write operation spanning multiple clock cycles; and
after receiving one or more data units of said data by said memory array, allow a subsequent burst write or read command to begin before completion of said burst write operation in progress;
an encoder operable to encode said data to be written to said memory array; and
a decoder coupled to said memory array and operable to check and correct said data previously encoded by said encoder and saved in said memory array.
2. The memory device of claim 1 further comprising:
a data latch coupled to said decoder, said data latch configured to latch decoded data from said decoder in response to an array read operation and configured to output latched data to said encoder in said burst write operation; and
a write buffer configured to receive said data from said encoder and provide said data for writing to said memory array.
3. The memory device of claim 2 , wherein while another burst write operation accessing a first location within another page of data is in progress, said memory device is operable to receive another burst read command initiating reading from a second location within said another page of data, said memory device being operable to continue executing said another burst write operation and to provide data associated with said another burst read operation from said data latch.
4. The memory device of claim 1 , wherein said memory array is made of a non-volatile memory.
5. The memory device of claim 1 , wherein said memory array is made of magnetic random access memory (MRAM).
6. The memory device of claim 1 , wherein said memory array is made of spin torque transfer magnetic random access memory (STTMRAM).
7. The memory device of claim 1 , wherein a write operation takes longer than a read operation.
8. The memory device of claim 1 , wherein said memory device is compliant with at least one version of double data rate (DDR) SDRAM Specification.
9. The memory device of claim 1 , wherein said memory device is compliant with at least one version of low power double data rate (LPDDR) Specification.
10. The memory device of claim 1 , wherein a version of double data rate (DDR) scheme is employed during burst write and burst read operations.
11. The memory device of claim 10 , wherein a double data rate 3 (DDR3) scheme is employed during burst write and burst read operations.
12. The memory device of claim 1 , wherein a version of low power double data rate (LPDDR) scheme is employed during burst write and burst read operations.
13. The memory device of claim 12 , wherein a low power double data rate 2 (LPDDR2) scheme is employed during burst write and burst read operations.