3D integrated circuit device

1. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said first transistor controls the supply of a ground or a power signal to said third transistor, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

2. The device according to claim 1 ,

wherein said second transistor and said third transistor are junction-less transistors.

3. The device according to claim 1 , further comprising:

a second transistor gate dielectric; and

a third transistor gate dielectric,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer.

4. The device according to claim 1 ,

wherein said second transistor and said third transistor each have a first gate and a second gate.

5. The device according to claim 1 ,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate, and

wherein said first gate is not connected to said second gate.

6. The device according to claim 1 ,

wherein said third transistor is controlled by a third control line,

wherein said second transistor is controlled by a second control line, and

wherein said first transistor is part of a control circuit controlling said second control line and third control line.

7. The device according to claim 1 ,

wherein said second transistor is self-aligned to said third transistor.

8. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor, said second transistor has a second transistor gate dielectric; and

a third transistor, said third transistor has a third transistor gate dielectric,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said second transistor and said third transistor are junction-less transistors,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

9. The device according to claim 8 , further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

a memory periphery circuit comprising said first transistor,

wherein said memory periphery circuits control said third memory cell and second memory cell.

10. The device according to claim 8 ,

wherein said second transistor is connected to said third transistor with an ohmic connection.

11. The device according to claim 8 ,

wherein said second transistor and said third transistor each have a first gate and a second gate.

12. The device according to claim 8 ,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate, and

wherein said first gate is not connected to said second gate.

13. The device according to claim 8 ,

wherein said third transistor is controlled by a third control line,

wherein said second transistor is controlled by a second control line, and

wherein said first transistor is part of a control circuit controlling said second control line and third control line.

14. The device according to claim 8 ,

wherein said second transistor is self-aligned to said third transistor.

15. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate,

wherein said first gate is not connected to said second gate, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

16. The device according to claim 15 , further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

a memory periphery circuit comprising said first transistor,

wherein said memory periphery circuit controls said third memory cell and second memory cell.

17. The device according to claim 15 ,

wherein said second transistor is connected to said third transistor with an ohmic connection.

18. The device according to claim 15 ,

wherein said second transistor and said third transistor are junction-less transistors.

19. The device according to claim 15 , further comprising:

a second transistor gate dielectric; and

a third transistor gate dielectric,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer.

20. The device according to claim 15 ,

wherein said second transistor is self-aligned to said third transistor.