IP Library Granted Patent US 10,224,256
Granted Patent B2
US 10,224,256 · App. 15/625,464 · Granted Mar 5, 2019

Manufacturing method of semiconductor package

Inventors: Hirokazu Machida (Sakai, JP); Kazuhiko Kitano (Sakai, JP)
Assignee: J-DEVICES CORPORATION
H01L23/142H01L21/4803H01L21/4846H01L21/4871H01L21/561H01L21/563H01L23/3128H01L23/5389H01L23/544H01L23/552H01L24/03H01L24/04H01L24/11H01L24/13H01L24/19H01L24/83H01L24/97H01L23/49816H01L24/32H01L24/73H01L24/92H01L2223/54426H01L2223/54486H01L2224/02311H01L2224/02379H01L2224/02381H01L2224/03914H01L2224/04105H01L2224/11013H01L2224/11334H01L2224/11849H01L2224/12105H01L2224/2919H01L2224/32245H01L2224/73267H01L2224/82039H01L2224/83132H01L2224/83192H01L2224/92244H01L2224/97
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Quick Facts
Patent No.
US 10,224,256
App. No.
15/625,464
Granted
Mar 5, 2019
Kind
B2
Abstract

A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

Claims (27)

1. A manufacturing method of a semiconductor package, comprising:

etching a first surface and a side surface of a base substrate, the base substrate including the first surface, a second surface opposed to the first surface and the side surface positioned between the first surface and the second surface, the base substrate containing at least one kind of metal;

precipitating a metal different from the at least one kind of metal contained in the base substrate on an entire surface of the first surface and an entire surface of the side surface;

disposing a semiconductor device on the second surface of the base substrate, the semiconductor device having an external terminal;

forming a resin insulating layer sealing the semiconductor device;

forming a first conductive layer on the resin insulating layer;

forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and

forming a conductive plating layer on the entire surface of the first surface of the base substrate on which the metal is precipitated and the entire surface of the side surface of the base substrate on which the metal is precipitated, on the first conductive layer and in the opening;

wherein a surface of the semiconductor device on which the external terminal is not provided faces the base substrate.

2. The manufacturing method of a semiconductor package according to claim 1 , wherein the base substrate is a stainless steel substrate.

3. The manufacturing method of a semiconductor package according to claim 2 , wherein the etching is wet etching using an etchant containing ions of the metal which is to be precipitated on the first surface and the side surface.

4. The manufacturing method of a semiconductor package according to claim 3 , wherein the metal precipitated on the first surface and the side surface has an ionization tendency smaller than an ionization tendency of the at least one kind of metal contained in the base substrate.

5. The manufacturing method of a semiconductor package according to claim 2 , wherein the conductive plating layer contains the same metal as the metal precipitated on the first surface and the side surface.

6. The manufacturing method of a semiconductor package according to claim 3 , wherein the conductive plating layer contains the same metal as the metal precipitated on the first surface and the side surface.

7. The manufacturing method of a semiconductor package according to claim 1 , wherein the metal precipitated on the first surface and the side surface has an ionization tendency smaller than an ionization tendency of the at least one kind of metal contained in the base substrate.

8. The manufacturing method of a semiconductor package according to claim 1 , wherein the conductive plating layer is formed by electroless plating.

9. The manufacturing method of a semiconductor package according to claim 1 , wherein the conductive plating layer contains the same metal as the metal precipitated on the first surface and the side surface.

10. The manufacturing method of a semiconductor package according to claim 1 , further comprising:

forming a second conductive layer by growing the conductive plating layer.

11. The manufacturing method of a semiconductor package according to claim 1 , wherein the resin insulating layer contains a filler.

12. The manufacturing method of a semiconductor package according to claim 11 , the filler contains an inorganic material.

13. The manufacturing method of a semiconductor package according to claim 1 , further comprising:

roughening a surface of the first conductive layer with laser light.

14. The manufacturing method of a semiconductor package according to claim 13 , wherein the opening is formed by irradiating the first conductive layer and the resin insulating layer with the laser light.

15. The manufacturing method of a semiconductor package according to claim 1 , wherein the etching is wet etching using an etchant containing ions of the metal which is to be precipitated on the first surface and the side surface.

16. The manufacturing method of a semiconductor package according to claim 15 , wherein the metal precipitated on the first surface and the side surface has an ionization tendency smaller than an ionization tendency of the at least one kind of metal contained in the base substrate.

17. The manufacturing method of a semiconductor package according to claim 2 , wherein the conductive plating layer contains the same metal as the metal precipitated on the first surface and the side surface.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 53597 FRAME: 184. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 5, 2021
From: J-DEVICES CORPORATION
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 055605/0060 →
CHANGE OF NAME Recorded Aug 25, 2020
From: J-DEVICES CO., LTD.
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 053597/0184 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2017
From: MACHIDA, HIROKAZU; KITANO, KAZUHIKO
To: J-DEVICES CORPORATION
Reel/Frame 042735/0793 →
Priority Claims (1)
JP 2016-121024 · Jun 17, 2016 · national
Continuity (1)
Related Publication 20170365534A1 · Dec 21, 2017