Integrating and isolating nFET and pFET nanosheet transistors on a substrate
View Patent ↗Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first sacrificial nanosheet and forming a first nanosheet stack over the first sacrificial nanosheet, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial nano sheets. The method further includes exposing a surface area of the first sacrificial nanosheet and exposing surface areas of the alternating channel nanosheets and sacrificial nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and sacrificial nanosheets. The method further includes applying an etchant to the exposed surface areas, wherein the etchant is selective based at least in part on the amount of surface area to which the etchant is applied.
1. A method of opening an insulation region during fabrication of a nanosheet channel field effect transistor (FET), the method comprising:
forming a first sacrificial nanosheet across from a major surface of a substrate;
forming a first nanosheet stack on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack comprises alternating channel nanosheets and sacrificial stack nanosheets;
exposing a surface area of the first sacrificial nano sheet;
exposing surface areas of the alternating channel nanosheets and surface areas of the alternating sacrificial stack nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and the sacrificial stack nanosheets; and
opening the insulation region by applying an etchant to the exposed surface area of the first sacrificial nanosheet, the exposed surface area of the alternating channel nanosheets, and the exposed surface areas of the alternating sacrificial stack nanosheets;
wherein the etchant is configured to include an etchant selectivity;
wherein the etchant selectivity is based at least in part on the type of material to which the etchant is applied;
wherein the etchant selectivity is further based at least in part on the amount of surface area to which the etchant is applied.
2. The method of claim 1 , wherein the first sacrificial nanosheet comprises silicon.
3. The method of claim 2 , wherein:
the alternating sacrificial stack nanosheets comprise silicon; and
the alternating channel nanosheets comprise silicon germanium.
4. The method of claim 3 , wherein the etchant comprises ammonium.
5. The method of claim 2 , wherein:
the alternating sacrificial stack nanosheets comprise silicon germanium; and
the alternating channel nanosheets comprise silicon.
6. The method of claim 5 , wherein the etchant comprises ammonium.
7. The method of claim 1 , wherein applying the etchant removes the first sacrificial nanosheet.
8. The method of claim 7 , wherein applying the etchant does not remove the alternating sacrificial stack nanosheets.
9. The method of claim 8 , wherein applying the etchant does not remove the alternating channel nanosheets.
10. The method of claim 9 further comprising forming a dielectric material in at least a portion of a space that was occupied by the first sacrificial nano sheet.
11. The method of claim 9 further comprising converting at least one of the alternating sacrificial stack nanosheets to a dielectric oxide.
12. The method of claim 11 further comprising forming a dielectric electric material in at least a portion of a space that was occupied by the first sacrificial nanosheet, wherein an insulating dielectric comprises the dielectric oxide and the dielectric material.
13. A method of opening insulation regions during the fabrication of nanosheet channel field effect transistors (FETs), the method comprising:
forming a substrate comprising a major surface having a first region and a second region;
forming a sacrificial nanosheet across from the major surface of the substrate, wherein the sacrificial nanosheet comprises a first sacrificial nanosheet across from the first region and a second sacrificial nanosheet across from the second region;
forming a nanosheet stack on an opposite side of the sacrificial nanosheet from the major surface of the substrate, wherein the nanosheet stack comprises a first nanosheet stack on an opposite side of the first sacrificial nanosheet from the first region, wherein the nanosheet stack further comprises a second nanosheet stack on an opposite side of the second sacrificial nanosheet from the second region, wherein the first nanosheet stack comprises alternating first channel nanosheets and first sacrificial stack nanosheets, wherein the second nanosheet stack comprises alternating second channel nanosheets and second sacrificial stack nanosheets;
exposing a surface area of the first sacrificial nano sheet;
exposing a surface area of the second sacrificial nanosheet;
exposing surface areas of the alternating first channel nanosheets and surface areas of the alternating first sacrificial stack nanosheets;
exposing surface areas of the alternating second channel nanosheets and surface areas of the alternating second sacrificial stack nanosheets;
wherein the exposed surface area of the first sacrificial nanosheet is greater than the exposed surface area of each of the alternating first channel nanosheets and each of the alternating first sacrificial stack nanosheets;
wherein the exposed surface area of the second sacrificial nanosheet is greater than the exposed surface area of each of the alternating second channel nanosheets and each of the alternating second sacrificial stack nanosheets; and
opening the insulation regions by applying an etchant to the exposed surface areas of the first sacrificial nanosheet, the second sacrificial nanosheet, the alternating first channel nanosheets and first sacrificial stack nanosheets, and the alternating second channel nanosheets and second sacrificial stack nanosheets;
wherein the etchant is configured to include an etchant selectivity;
wherein the etchant selectivity is based at least in part on the type of material to which the etchant is applied;
wherein the etchant selectivity is further based at least in part on the amount of surface area to which the etchant is applied.
14. The method of claim 13 , wherein:
the first sacrificial nanosheet and the second sacrificial nanosheet comprise silicon;
the alternating first sacrificial stack nanosheets comprise silicon; and
the alternating first channel stack nanosheets of the first region comprise silicon germanium.
15. The method of claim 14 , wherein:
the alternating second sacrificial stack nanosheets comprise silicon germanium; and
the alternating second channel nanosheets comprise silicon.
16. The method of claim 15 , wherein the etchant comprises ammonium.
17. The method of claim 13 , wherein:
the etchant removes the first sacrificial nanosheet and the second sacrificial nanosheet; and
the etchant does not remove the alternating first sacrificial nanosheets, the alternating first channel stack nanosheets, the alternating second sacrificial stack nanosheets over the second region, and the alternating channel nanosheets over the second region.
18. The method of claim 13 further comprising:
forming a dielectric in at least a portion of a first space that was occupied by the first sacrificial nanosheet; and
forming the dielectric in at least a portion of a second space that was occupied by the second sacrificial nanosheet.
19. The method of claim 13 , wherein forming the nanosheet stack comprises:
forming the first nanosheet stack on the opposite side of the sacrificial nanosheet from the first region and the second region;
removing the first nanosheet stack on the opposite side of the sacrificial nanosheet from the second region; and
forming the second nanosheet stack on the opposite side of the sacrificial nanosheet from the second region.