Semiconductor device and method for manufacturing the same

1. A method for manufacturing a semiconductor device, comprising:

forming a fin over a substrate;

forming a liner layer over the fin;

etching the isolation dielectric to form an STI region having a top surface lower than a top end of the liner layer;

after etching the isolation dielectric, etching the liner layer to expose a channel region of the fin;

forming a spacer around the channel region of the fin;

after forming the spacer, etching the STI region and the liner layer to expose a source region of the fin;

growing an epitaxy feature from the exposed source region of the fin;

removing the spacer to expose the channel region of the fin; and

forming a gate stack around the exposed channel region of the fin.

2. The method of claim 1 , wherein the spacer remains on the channel region of the fin during etching the STI region and the liner layer.

3. The method of claim 1 , wherein the forming of the liner layer is performed prior to the forming of the spacer.

4. The method of claim 1 , further comprising:

forming a dielectric material over the substrate to cover the spacer and the epitaxy feature; and

recessing the dielectric material to expose the spacer prior to the removing the spacer.

5. The method of claim 4 , wherein the recessing the dielectric material is performed by using an etching process.

6. The method of claim 1 , wherein a portion of the liner layer remains around the STI region after etching the liner layer to expose the channel region.

7. The method of claim 1 , wherein forming the spacer comprises:

depositing a spacer layer having a lateral portion extending past an interface between the liner layer and the STI region and a vertical portion extending along a sidewall of the channel region; and

etching the spacer layer to remove the lateral portion from the STI region, while leaving the vertical portion on the sidewall of the channel region.

8. The method of claim 1 , further comprising:

forming a dielectric material laterally around the epitaxy feature prior to removing the spacer.

9. The method of claim 8 , wherein the dielectric material remains laterally around the epitaxy feature after the spacer is removed.

10. A method for manufacturing a semiconductor device, comprising:

forming a fin over a substrate;

forming a protective layer to enclose a channel region of the fin;

forming a shallow trench isolation (STI) dielectric around a source region of the fin;

etching back the STI dielectric to a level lower than the source region of the fin;

after etching back the STI dielectric, growing a first epitaxy feature from the source region of the fin;

after growing the first epitaxy feature, forming a dielectric material over a sidewall of the first epitaxy feature and a sidewall of the protective layer;

etching back the dielectric material to expose the sidewall of the protective layer;

after etching back the dielectric material, removing the protective layer to expose the enclosed channel region after the growing the first epitaxy feature; and

forming a gate stack to enclose the exposed channel region.

11. The method of claim 10 , wherein the STI dielectric is formed around the source region before forming the protective layer around the channel region.

12. The method of claim 10 , further comprising:

etching the gate stack such that a drain region of the fin protrudes above the gate stack; and

growing a second epitaxy feature from a top surface and sidewalls of the drain region.

13. The method of claim 12 , wherein the second epitaxy feature has a different shape than the first epitaxy feature.

14. A method for manufacturing a semiconductor device, comprising:

forming a fin over a substrate;

growing a first epitaxy feature from a source region of the fin below a channel region of the fin;

depositing a dielectric material around a sidewall of the first epitaxy feature;

etching back the dielectric material, while leaving a portion of the dielectric material on a sidewall of the first epitaxy feature;

after etching back the dielectric material, forming a gate stack to surround the channel region of the fin; and

after the forming of the gate stack, growing a second epitaxy feature from a drain region of the fin.

15. The method of claim 14 , further comprising:

forming a spacer covering the channel region of the fin prior to growing the first epitaxy feature.

16. The method of claim 14 , wherein growing the first epitaxy feature is performed such that the first epitaxy feature has an upward facing facet, a downward facing facet and a vertical facet connecting the upward facing facet and the downward facing facet.

17. The method of claim 14 , further comprising:

forming a liner layer to cover the fin; and

removing a portion of the liner layer to expose the source region of the fin, wherein growing the first epitaxy feature is performed such that the first epitaxy feature is grown from the exposed source region of the fin.

18. The method of claim 14 , further comprising:

prior to growing the second epitaxy feature, etching the gate stack such that the drain region of the fin protrudes above the gate stack.

19. The method of claim 14 , further comprising:

prior to depositing the dielectric material over the fin, forming a spacer around the channel region; and

after etching back the dielectric material, removing the spacer from the channel region.

20. The method of claim 19 , wherein after removing the spacer from the channel region, the sidewall of the first epitaxy feature remains covered by the dielectric material.