Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures
Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.
1. A semiconductor structure comprising:
a semiconductor layer on a substrate;
a non-planar field effect transistor on the semiconductor layer and comprising:
source/drain regions;
at least one channel region positioned laterally between the source/drain regions; and
a gate structure adjacent to the channel region; and
layers of oxide material electrically isolating and physically separating the source/drain regions from the semiconductor layer,
each layer of oxide material having a bottom surface immediately adjacent to the semiconductor layer and a top surface immediately adjacent to a source/drain region,
the channel region comprising any one of a first semiconductor material and a second semiconductor material that is different from the first semiconductor material,
the semiconductor layer comprising the second semiconductor material, and
the oxide material comprises an oxide of the second semiconductor material.
2. The semiconductor structure of claim 1 , wherein the layers of oxide material reduce source-to-drain leakage below the channel region.
3. The semiconductor structure of claim 1 ,
the substrate comprising the first semiconductor material,
the first semiconductor material comprising silicon,
the second semiconductor material comprising silicon germanium, and
the layers of oxide material comprising layers of silicon germanium oxide.
4. The semiconductor structure of claim 1 ,
the non-planar field effect transistor is a fin-type field effect transistor,
the channel region is a single fin-shaped channel region comprising the first semiconductor material immediately adjacent to a top surface of the semiconductor layer, and
the gate structure is adjacent to opposing sides of the single fin-shaped channel region.
5. The semiconductor structure of claim 1 ,
the non-planar field effect transistor is a nanowire-type field effect transistor,
the at least one channel region comprising at least one nanowire physically separated from a top surface of the semiconductor layer, and
the gate structure wrapping around the at least one nanowire.
6. The semiconductor structure of claim 1 , the layers of oxide material being on a horizontal surface of the semiconductor layer.
7. The semiconductor structure of claim 1 , the semiconductor layer having a top surface and recesses in the top surface on opposing sides of the gate structure, the layers of oxide material being on vertical and horizontal surfaces of the semiconductor layer within the recesses and the source/drain regions being on the layers of oxide material and extending vertically above the top surface of the semiconductor layer.
8. A semiconductor structure comprising:
a semiconductor layer on a substrate;
a non-planar field effect transistor on the semiconductor layer and comprising:
source/drain regions;
at least one channel region positioned laterally between the source/drain regions; and
a gate structure adjacent to the channel region; and
layers of oxide material electrically isolating and physically separating the source/drain regions from the semiconductor layer,
each layer of oxide material having a bottom surface immediately adjacent to the semiconductor layer and a top surface immediately adjacent to a source/drain region,
the source/drain regions being aligned above the layers of oxide material, respectively, and the source/drain regions and the layers of oxide materials having essentially equal lengths as measured from an inner end adjacent to the channel region to an outer end opposite the inner end,
the channel region comprising any one of a first semiconductor material and a second semiconductor material that is different from the first semiconductor material,
the semiconductor layer comprising the second semiconductor material, and
the oxide material comprises an oxide of the second semiconductor material.
9. The semiconductor structure of claim 8 , wherein the layers of oxide material reduce source-to-drain leakage below the channel region.
10. The semiconductor structure of claim 8 ,
the substrate comprising the first semiconductor material,
the first semiconductor material comprising silicon,
the second semiconductor material comprising silicon germanium, and
the layers of oxide material comprising layers of silicon germanium oxide.
11. The semiconductor structure of claim 8 ,
the non-planar field effect transistor is a fin-type field effect transistor,
the channel region is a single fin-shaped channel region comprising the first semiconductor material immediately adjacent to a top surface of the semiconductor layer, and
the gate structure is adjacent to opposing sides of the single fin-shaped channel region.
12. The semiconductor structure of claim 8 , the layers of oxide material being on a horizontal surface of the semiconductor layer.
13. The semiconductor structure of claim 8 , the semiconductor layer having a top surface and recesses in the top surface on opposing sides of the gate structure, the layers of oxide material being on vertical and horizontal surfaces of the semiconductor layer within the recesses and the source/drain regions being on the layers of oxide material and extending vertically above the top surface of the semiconductor layer.
14. A semiconductor structure comprising:
a silicon germanium layer on a silicon substrate;
a non-planar field effect transistor on the silicon germanium layer and comprising:
epitaxial silicon source/drain regions;
a silicon channel region positioned laterally between the epitaxial silicon source/drain regions; and
a gate structure adjacent to the silicon channel region; and
layers of silicon germanium oxide electrically isolating and physically separating the epitaxial silicon source/drain regions from the silicon germanium layer,
each layer of silicon germanium oxide having a bottom surface immediately adjacent to the silicon germanium layer and a top surface immediately adjacent to an epitaxial silicon source/drain region,
the epitaxial silicon source/drain regions being aligned above the layers of silicon germanium oxide, respectively, and the epitaxial source/drain regions and the layers of silicon germanium oxide having essentially equal lengths as measured from an inner end adjacent to the silicon channel region to an outer end opposite the inner end.
15. The semiconductor structure of claim 14 , wherein the layers of silicon germanium oxide reduce source-to-drain leakage below the silicon channel region.
16. The semiconductor structure of claim 14 ,
the non-planar field effect transistor is a fin-type field effect transistor,
the silicon channel region is a single fin-shaped silicon channel region immediately adjacent to the top surface of the silicon germanium layer, and
the gate structure is adjacent to opposing sides of the single fin-shaped silicon channel region.
17. The semiconductor structure of claim 14 , the layers of silicon germanium oxide being on a horizontal surface of the silicon germanium layer.
18. The semiconductor structure of claim 14 , the silicon germanium layer having recesses in the top surface on opposing sides of the gate structure, the layers of silicon germanium oxide being on vertical and horizontal surfaces of the silicon germanium layer within the recesses and the epitaxial silicon source/drain regions being on the layers of silicon germanium oxide.