Fan-out semiconductor package
View Patent ↗A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.
1. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and
a resin layer disposed between the encapsulant and the second interconnection member and contacting at least portions of side surfaces of the protrusion bump,
wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad,
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer and contacting the second interconnection member, and
the resin layer contacts at least portions of side surfaces of the third redistribution layer.
2. The fan-out semiconductor package of claim 1 , wherein an interface between the second interconnection member and the resin layer is substantially at the same level as an interface between the second interconnection member and the protrusion bump.
3. The fan-out semiconductor package of claim 1 , wherein an interface between the second interconnection member and the resin layer is substantially at the same level as an interface between the second interconnection member and the third redistribution layer.
4. The fan-out semiconductor package of claim 1 , wherein the first interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer.
5. The fan-out semiconductor package of claim 1 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.
6. The fan-out semiconductor package of claim 1 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.
7. The fan-out semiconductor package of claim 1 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer embedded in a first surface of the first insulating layer, and a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer, and
the resin layer contacts at least portions of the embedded first redistribution layer.
8. The fan-out semiconductor package of claim 7 , wherein an interface between the second interconnection member and the resin layer is substantially at the same level as an interface between the second interconnection member and the first insulating layer.
9. The fan-out semiconductor package of claim 7 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer.
10. The fan-out semiconductor package of claim 9 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.
11. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and side surfaces of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and having a redistribution layer electrically connected to the connection pad of the semiconductor chip; and
a cover layer disposed on the encapsulant and covering the inactive surface of the semiconductor chip,
wherein the first interconnection member includes a first redistribution layer contacting the second interconnection member and a second redistribution layer contacting the cover layer,
the first redistribution layer and the second redistribution layer are electrically connected to the connection pad of the semiconductor chip, and
the first redistribution layer has a thickness smaller than that of the second redistribution layer.
12. The fan-out semiconductor package of claim 11 , wherein an interface between the second interconnection member and the first redistribution layer is substantially at the same level as an interface between the second interconnection member and the protrusion bump.