IP Library Granted Patent US 10,304,992
Granted Patent B2
US 10,304,992 · App. 15/634,178 · Granted May 28, 2019

Multicolor LED and method of fabricating thereof

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Quick Facts
Patent No.
US 10,304,992
App. No.
15/634,178
Granted
May 28, 2019
Kind
B2
Abstract

A device includes a support including at least a first area and a second area, and a plurality of first light emitting devices located over the first area of the support, each first light emitting device containing a first growth template including a first nanostructure, and each first light emitting device has a first peak emission wavelength. The device also includes a plurality of second light emitting devices located over the second area of the support, each second light emitting device containing a second growth template including a second nanostructure, and each second light emitting device has a second peak emission wavelength different from the first peak emission wavelength. Each first growth template differs from each second growth template.

Claims (31)

1. A III-V semiconductor nanowire device, comprising:

a plurality of III-V nanopyramids extending through first apertures in a first area of a growth mask located over a substrate; and

a plurality of III-V nanowires extending through second apertures in a second area of the growth mask,

wherein:

the first apertures are larger than the second apertures; and

a ratio of p-planes to m-planes in the plurality of III-V nanopyramids is different from a ratio of p-planes to m-planes in the plurality of III-V nanowires.

2. The device of claim 1 , wherein the plurality of III-V nanopyramids have a smaller height than the III-V nanowires.

3. The device of claim 2 , wherein the plurality of III-V nanowires have a height of 0.1 to 5 microns.

4. The device of claim 1 , wherein each first aperture is spaced further apart from adjacent first apertures than each second aperture is spaced from adjacent second apertures.

5. The device of claim 1 , wherein the growth mask comprises a silicon nitride layer.

6. The device of claim 1 , wherein:

each of the plurality of III-V nanopyramids comprises a first nanowire core; and

each of the plurality of III-V nanowires comprises a second nanowire core.

7. The device of claim 6 , further comprising:

at least one first template layer around the first nanowire core, such that the first template layer extends laterally beyond the first aperture over the growth mask;

at least one second template layer around the second nanowire core, such that the second template layer extends laterally beyond the second aperture over the growth mask;

first and second active regions located on respective first and second template layers; and

first and second junction forming elements located on respective first and second active regions to form respective first and second light emitting devices.

8. The device of claim 7 , wherein:

each first active region comprises at least one first quantum well having a first band gap;

each second active region comprises at least one second quantum well having a second band gap different from the first band gap;

each first quantum well contains a higher amount of indium and a longer peak emission wavelength than each second quantum well due to the difference in the p-plane facet area.

9. The device of claim 8 , wherein:

each first nanowire core comprises a first conductivity type semiconductor material;

each second nanowire core comprises the first conductivity type semiconductor material;

each first junction forming element comprises a semiconductor material of a second conductivity type different from the first conductivity type to form a p-n or p-i-n junction with the first growth template and the first active region; and

each second junction forming element comprises a semiconductor material of the second conductivity type different from the first conductivity type to form a p-n or p-i-n junction with the second growth template and the second active region.

10. The device of claim 9 , wherein:

each first and second nanowire core comprises a n-type GaN nanowire core;

each first and second quantum well comprises an indium gallium nitride shell; and

each first and second junction forming element comprise a p-type GaN semiconductor shell.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2024
From: GLO TECHNOLOGIES LLC
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068297/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2023
From: SYSONAN, INC.
To: GLO TECHNOLOGIES LLC
Reel/Frame 065178/0210 →
CHANGE OF NAME Recorded Oct 5, 2023
From: NANOSYS, INC.
To: SYSONAN, INC.
Reel/Frame 065156/0416 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT RECORDED AT REEL 059569 / FRAME 0840 Recorded Sep 7, 2023
From: FORTRESS CREDIT CORP.,
To: NANOSYS, INC.
Reel/Frame 064836/0263 →
SECURITY INTEREST Recorded Apr 1, 2022
From: NANOSYS, INC.
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 059569/0840 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 13, 2021
From: GLO AB
To: NANOSYS, INC.
Reel/Frame 057184/0564 →
RELEASE OF SECURITY INTEREST Recorded Apr 12, 2021
From: HERCULES CAPITAL, INC.
To: GLO AB
Reel/Frame 057210/0690 →
SECURITY INTEREST Recorded Jan 23, 2019
From: GLO AB
To: HERCULES CAPITAL INC.
Reel/Frame 048110/0063 →
ASSIGNMENT OF IP SECURITY AGREEMENT Recorded Dec 12, 2018
From: GLO AB
To: HERCULES CAPITAL, INC., AS ADMINISTRATIVE AGENT
Reel/Frame 049042/0527 →