Write verification and resistive state determination based on cell turn-on characteristics for resistive random access memory

1. A method of operating a resistive memory device, comprising:

providing a resistive memory device including an array of resistive memory cells, wherein each of the resistive memory cells comprises a resistive memory material having at least two different resistive states;

programming a selected resistive memory cell with a selected resistive state; and

verifying a programmed state of the selected resistive memory cell by:

determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state;

if the measured electrical current at the preset read voltage is out of specification, then iteratively applying a plurality of modified read voltages across the selected resistive memory cell and selecting a modified read voltage that provides a preset level of electrical current through the selected resistive memory cell as a measured threshold voltage, and then determining whether the measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state;

identifying the selected resistive memory cell as an operational resistive memory cell if at least one of the measured electrical current and the measured threshold voltage is within a respective specification for the selected resistive state; and

identifying the selected resistive memory cell as a non-functional resistive memory cell if both the measured electrical current and the measured threshold voltage are outside the respective specification for the selected resistive state;

wherein:

the selected resistive memory cell comprises a barrier modulated cell of a resistive random access memory (ReRAM) device; and

the barrier modulated cell comprises a metal oxide material having at least two states having different resistivity, a barrier material and an interfacial barrier oxide located between the metal oxide material and the barrier material.

2. The method of claim 1 , wherein the preset read voltage is the same as a read voltage for a read operation that determines a resistive state of each of the resistive memory cells.

3. The method of claim 1 , wherein the preset level of electrical current is less than 0.01 times a maximum reset verification current threshold for a high resistive reset state for each of the resistive memory cells within the array of resistive memory cells.

4. The method of claim 1 , further comprising:

programming a plurality of resistive memory cells with a respective selected resistive state;

sequentially selecting each resistive memory cell within the plurality of resistive memory cells;

determining whether the measured electrical current at the preset read voltage for the plurality of resistive memory cells is within electrical current specification for the selected resistive state; and

if the measured electrical current at the preset read voltage is out of specification for a first set of resistive memory cells of the plurality of resistive memory cells, then determining whether a measured threshold voltage for the first set of memory cells is within threshold voltage specification for the selected resistive state.

5. The method of claim 4 , further comprising:

generating a list of non-functional resistive memory cells based on the steps of determining; and

rewriting data assigned to the non-functional resistive memory cells to an additional set of resistive memory cells.

6. The method of claim 1 , wherein the metal oxide material comprises sub-stoichiometric titanium oxide (TiO 2-δ ), the barrier material comprises amorphous silicon and the interfacial barrier oxide comprises silicon oxide.

7. The method of claim 6 , wherein programming the selected resistive memory cell comprises programming the barrier modulated cell into a reset state by applying a voltage to the barrier modulated cell to provide oxygen interstitials from the interfacial barrier oxide to the TiO 2-δ and increase a resistance of the selected resistive memory cell.

8. The method of claim 6 , wherein programming the selected resistive memory cell comprises programming the barrier modulated cell into a set state by applying a voltage to the barrier modulated cell to generate oxygen interstitial and oxygen vacancy pairs in the TiO 2-δ , and to provide oxygen interstitials away from the TiO 2-δ to the interfacial barrier oxide and decrease a resistance of the selected resistive memory cell.

9. A method of operating a resistive memory device, comprising:

providing a resistive memory device including an array of resistive memory cells, wherein each of the resistive memory cells comprises a resistive memory material having at least two different resistive states;

programming a selected resistive memory cell with a selected resistive state; and

verifying a programmed state of the selected resistive memory cell by:

determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state;

if the measured electrical current at the preset read voltage is out of specification, then determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state;

identifying the selected resistive memory cell as an operational resistive memory cell if at least one of the measured electrical current and the measured threshold voltage is within a respective specification for the selected resistive state; and

identifying the selected resistive memory cell as a non-functional resistive memory cell if both the measured electrical current and the measured threshold voltage are outside the respective specification for the selected resistive state;

wherein:

the selected resistive memory cell comprises a barrier modulated cell of a resistive random access memory (ReRAM) device; and

the barrier modulated cell comprises a metal oxide material having at least two states having different resistivity, a barrier material and an interfacial barrier oxide located between the metal oxide material and the barrier material;

wherein the measured threshold voltage is generated by determining an electrical bias voltage across the selected resistive memory cell that provides a preset level of electrical current through the selected resistive memory cell;

wherein the preset level of electrical current is less than 0.01 times a maximum reset verification current threshold for a high resistive reset state for each of the resistive memory cells within the array of resistive memory cells.

10. The method of claim 9 , wherein the preset read voltage is the same as a read voltage for a read operation that determines a resistive state of each of the resistive memory cells.

11. The method of claim 9 , further comprising:

programming a plurality of resistive memory cells with a respective selected resistive state;

sequentially selecting each resistive memory cell within the plurality of resistive memory cells;

determining whether the measured electrical current at the preset read voltage for the plurality of resistive memory cells is within electrical current specification for the selected resistive state; and

if the measured electrical current at the preset read voltage is out of specification for a first set of resistive memory cells of the plurality of resistive memory cells, then determining whether a measured threshold voltage for the first set of memory cells is within threshold voltage specification for the selected resistive state.

12. The method of claim 11 , further comprising:

generating a list of non-functional resistive memory cells based on the steps of determining; and

rewriting data assigned to the non-functional resistive memory cells to an additional set of resistive memory cells.

13. The method of claim 9 , wherein the metal oxide material comprises sub-stoichiometric titanium oxide (TiO 2-δ ), the barrier material comprises amorphous silicon and the interfacial barrier oxide comprises silicon oxide.

14. The method of claim 13 , wherein programming the selected resistive memory cell comprises programming the barrier modulated cell into a reset state by applying a voltage to the barrier modulated cell to provide oxygen interstitials from the interfacial barrier oxide to the TiO 2-δ and increase a resistance of the selected resistive memory cell.

15. The method of claim 13 , wherein programming the selected resistive memory cell comprises programming the barrier modulated cell into a set state by applying a voltage to the barrier modulated cell to generate oxygen interstitial and oxygen vacancy pairs in the TiO 2-δ and to provide oxygen interstitials away from the TiO 2-δ to the interfacial barrier oxide and decrease a resistance of the selected resistive memory cell.