IP Library Granted Patent US 10,304,927
Granted Patent B2
US 10,304,927 · App. 15/640,966 · Granted May 28, 2019

Selective germanium p-contact metalization through trench

Inventors: Glenn A. Glass (Portland, OR); Anand S. Murthy (Portland, OR); Tahir Ghani (Portland, OR)
Assignee: INTEL CORPORATION
H01L29/0676H01L21/02532H01L21/28512H01L21/28525H01L21/3215H01L21/76831H01L23/535H01L27/092H01L27/0924H01L29/0615H01L29/086H01L29/0847H01L29/165H01L29/167H01L29/36H01L29/41791H01L29/42392H01L29/45H01L29/456H01L29/4966H01L29/6659H01L29/66477H01L29/66545H01L29/66628H01L29/66636H01L29/66681H01L29/66931H01L29/7785H01L29/78H01L29/785H01L29/7816H01L29/7833H01L29/7848H01L29/7851
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Quick Facts
Patent No.
US 10,304,927
App. No.
15/640,966
Granted
May 28, 2019
Kind
B2
Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Claims (36)

1. A semiconductor device, comprising:

a semiconductor fin;

a gate structure adjacent to a top and opposing sides of the semiconductor fin, the gate structure including a gate dielectric and a gate electrode, the gate dielectric between the gate electrode and at least a portion of the semiconductor fin;

a source region and a drain region, the source region and the drain region each comprising silicon, germanium, and a p-type dopant, the source region and the drain region each having an overall thickness that includes a first graded portion, a second graded portion, and a substantially fixed portion between the first and second graded portions, wherein

at least one of the first graded portions has a germanium concentration that is graded from a base level concentration to a first level concentration, and

at least one of the second graded portions has a germanium concentration that is graded from the first level concentration to a second level that is in excess of 50 atomic %, the first level being higher than the base level, and the second level being higher than the first level; and

first and second contact structures on the source region and the drain region, respectively, the first and second contact structures each including titanium, nitrogen, and tungsten.

2. The semiconductor device of claim 1 , wherein the base level concentration of germanium is about 0 atomic %, and the first level concentration of germanium is about 30 atomic %.

3. The semiconductor device of claim 1 , wherein the first and second contact structures each include a layer of titanium on the corresponding source or drain region, a layer of titanium nitride on the layer of titanium, and a layer of tungsten on the layer of titanium nitride.

4. The semiconductor device of claim 1 , wherein the overall thickness of the source region is the distance between a bottom of the first contact structure and a bottom of the source region, and is in the range of 50 to 250 nm, and the second graded portion of the source region has a thickness in the range of 3 to 12 nm.

5. The semiconductor device of claim 4 , wherein the second graded portion of the source region has a thickness in the range of 5 to 10 nm.

6. The semiconductor device of claim 1 , wherein the overall thickness of the drain region is the distance between a bottom of the second contact structure and a bottom of the drain region, and is in the range of 50 to 250 nm, and the second graded portion of the drain region has a thickness in the range of 3 to 12 nm.

7. The semiconductor device of claim 6 , wherein the second graded portion of the drain region has a thickness in the range of 5 to 10 nm.

8. The semiconductor device of claim 1 , further comprising:

first and second recesses in the semiconductor fin, wherein the source region is at least partially in the first recess and the drain region is at least partially in the second recess.

9. The semiconductor device of claim 8 , further comprising first and second gate spacers arranged in opposing fashion so that at least part of the gate electrode is between the first and second gate spacers, wherein one or more of the first and second recesses extends under a corresponding one of the first and second gate spacers.

10. The semiconductor device of claim 1 , wherein at least one of the substantially fixed portions has a lowest concentration level of germanium that is within 20% of a highest concentration level of germanium in that fixed portion.

11. The semiconductor device of claim 1 , wherein at least one of the substantially fixed portions has a lowest concentration level of germanium that is within 10% of a highest concentration level of germanium in that fixed portion.

12. A semiconductor device, comprising:

a semiconductor fin;

a gate structure adjacent to a top and opposing sides of the semiconductor fin, the gate structure including a gate dielectric and a gate electrode, the gate dielectric between the gate electrode and at least a portion of the semiconductor fin;

a source structure and a drain structure, the source structure and the drain structure each comprising silicon, germanium, and a p-type dopant, the source structure and the drain structure each having an overall thickness that includes a first graded portion, a second graded portion, and a substantially fixed portion between the first and second graded portions, wherein

at least one of the first graded portions has a germanium concentration that is graded from a base level concentration to a first level concentration, and

at least one of the second graded portions has a germanium concentration that is graded from the first level concentration to a second level, the first level being higher than the base level, and the second level being higher than the first level; and

first and second contact structures on the source structure and the drain structure, respectively, the first and second contact structures each including a layer of titanium on the corresponding source or drain structure, a layer of titanium nitride on the layer of titanium, and a layer of tungsten on the layer of titanium nitride;

wherein the overall thickness of the source structure is the distance between a bottom of the first contact structure and a bottom of the source structure, and is in the range of 50 to 250 nm, and the second graded portion of the source structure has a thickness in the range of 3 to 12 nm; and

wherein the overall thickness of the drain structure is the distance between a bottom of the second contact structure and a bottom of the drain structure, and is in the range of 50 to 250 nm, and the second graded portion of the drain structure has a thickness in the range of 3 to 12 nm.

13. The semiconductor device of claim 12 , wherein the base level concentration of germanium is about 0 atomic %, and the first level concentration of germanium is about 30 atomic %.

14. The semiconductor device of claim 12 , wherein the second level is in excess of 50 atomic %.

15. The semiconductor device of claim 12 , wherein the second graded portion of the source structure has a thickness in the range of 5 to 10 nm.

16. The semiconductor device of claim 12 , wherein the second graded portion of the drain structure has a thickness in the range of 5 to 10 nm.

17. The semiconductor device of claim 12 , further comprising:

first and second recesses in the semiconductor fin, wherein the source structure is at least partially in the first recess and the drain structure is at least partially in the second recess.

18. The semiconductor device of claim 17 , further comprising first and second gate spacers arranged in opposing fashion so that at least part of the gate electrode is between the first and second gate spacers, wherein one or more of the first and second recesses extends under a corresponding one of the first and second gate spacers.

19. The semiconductor device of claim 12 , wherein at least one of the substantially fixed portions has a lowest concentration level of germanium that is within 20% of a highest concentration level of germanium in that fixed portion.

20. The semiconductor device of claim 12 , wherein at least one of the substantially fixed portions has a lowest concentration level of germanium that is within 10% of a highest concentration level of germanium in that fixed portion.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2025
From: DAEDALUS PRIME LLC
To: MEDIATEK INC.
Reel/Frame 073948/0951 →
CORRECTIVE ASSIGNMENT TO CORRECT THE US PATENT 10,592,626 SHOULD HAVE BEEN IDENTIFIED AS 10,593,626. PREVIOUSLY RECORDED ON REEL 060392 FRAME 0603. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 18, 2023
From: INTEL CORPORATION
To: DAEDALUS PRIME LLC
Reel/Frame 063695/0134 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2023
From: INTEL CORPORATION
To: DAEDALUS PRIME LLC
Reel/Frame 062746/0654 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2022
From: INTEL CORPORATION
To: DAEDALUS PRIME LLC
Reel/Frame 060392/0603 →
Continuity (5)
Continuation 15162551 · May 23, 2016
Continuation 14807285 · Jul 23, 2015
Continuation 13990238
Continuation In Part 12975278 · Dec 21, 2010
Related Publication 20170373147A1 · Dec 28, 2017