IP Library Granted Patent US 10,008,578
Granted Patent B1
US 10,008,578 · App. 15/642,324 · Granted Jun 26, 2018

Semiconductor device and method for fabricating the same

Inventors: Hao-Ming Lee (Hsinchu County, TW); Sheng-Hao Lin (Hsinchu County, TW); Hsin-Yu Chen (Nantou County, TW); Shou-Wei Hsieh (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/4991H01L21/28088H01L29/4966H01L29/66545
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Quick Facts
Patent No.
US 10,008,578
App. No.
15/642,324
Granted
Jun 26, 2018
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

Claims (14)

1. A semiconductor device, comprising:

a metal gate on a substrate, wherein the metal gate comprises:

a high-k dielectric layer;

a work function metal layer on the high-k dielectric layer; and

a metal layer on the work function metal layer;

a spacer around the metal gate; and

an air gap between the work function metal layer and the spacer and contacts the high-k dielectric layer directly.

2. The semiconductor device of claim 1 , wherein the high-k dielectric layer and the work function metal layer are U-shaped.

3. The semiconductor device of claim 1 , wherein a top surface of the metal layer is higher than a top surface of the work function metal layer.

4. The semiconductor device of claim 1 , wherein a top surface of the work function metal layer is higher than a top surface of the high-k dielectric layer.

5. The semiconductor device of claim 1 , further comprising a hard mask on the work function metal layer and the metal layer.

6. The semiconductor device of claim 5 , wherein the air gap is between the hard mask and the high-k dielectric layer.

7. The semiconductor device of claim 5 , further comprising an interlayer dielectric (ILD) layer around the spacer.

8. The semiconductor device of claim 7 , wherein the top surfaces of the hard mask and the ILD layer are coplanar.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: LEE, HAO-MING; LIN, SHENG-HAO; CHEN, HSIN-YU; HSIEH, SHOU-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 042912/0471 →
Priority Claims (1)
TW 106118681 A · Jun 6, 2017 · national
Cited By (2)
US 12,400,910 US 12,713,643