IP Library Granted Patent US 10,007,460
Granted Patent B2
US 10,007,460 · App. 15/643,501 · Granted Jun 26, 2018

Flash memory controller

Inventors: Tsung-Chieh Yang (Hsinchu, TW); Chun-Chieh Kuo (Taipei, TW); Ching-Hui Lin (Taipei, TW); Yang-Chih Shen (Taipei, TW)
Assignee: Silicon Motion Inc.
G06F3/0634G06F3/0604G06F3/064G06F3/0679G06F12/0246G11C11/5628G11C11/5642G06F2212/7201G06F2212/7206Y02D10/13
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Quick Facts
Patent No.
US 10,007,460
App. No.
15/643,501
Granted
Jun 26, 2018
Kind
B2
Abstract

A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Claims (21)

1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a plurality of blocks, and the flash memory controller comprising:

a communication interface for receiving data from a host device; and

a processing circuit, coupled with the communication interface and the flash memory module, for dynamically determining a voltage range of a plurality of program threshold voltage intervals according to an amount of stored data in the flash memory module, and using the plurality of program threshold voltage intervals to write the data into one of the blocks.

2. The flash memory controller of claim 1 , wherein the processing circuit determines a first voltage range if the amount of stored data in the flash memory module is less than a first threshold, and the processing circuit determines a second voltage range if the amount of stored data in the flash memory module is greater than a first threshold, and the second voltage range is greater than the first voltage range.

3. The flash memory controller of claim 2 , wherein the plurality of data blocks are realized by triple-level cells (TLCs), and the blocks supports eight program threshold voltage intervals.

4. The flash memory controller of claim 3 , wherein if the amount of stored data in the flash memory module is less than the first threshold, the processing circuit uses only two of the program threshold voltage intervals within the first voltage range to write the data into the one of the blocks; and if the amount of stored data in the flash memory module is greater than the first threshold, the processing circuit uses at least four of the program threshold voltage intervals within the second voltage range to write the data into the one of the blocks.

5. The flash memory controller of claim 3 , wherein if the amount of stored data in the flash memory module is less than the first threshold, the processing circuit uses only two of the program threshold voltage intervals within the first voltage range to write the data into the one of the blocks; and if the amount of stored data in the flash memory module is greater than the first threshold, the processing circuit uses eight program threshold voltage intervals within the second voltage range to write the data into the one of the blocks.

6. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of blocks, and the method comprising:

receiving data from a host device; and

dynamically determining a voltage range of a plurality of program threshold voltage intervals according to an amount of stored data in the flash memory module; and

using the plurality of program threshold voltage intervals to write the data into one of the blocks.

7. The method of claim 6 , wherein the step of dynamically determining the voltage range of the plurality of program threshold voltage intervals according to the amount of stored data in the flash memory module comprises:

determining a first voltage range if the amount of stored data in the flash memory module is less than a first threshold; and

determining a second voltage range if the amount of stored data in the flash memory module is greater than a first threshold, wherein the second voltage range is greater than the first voltage range.

8. The method of claim 7 , wherein the plurality of data blocks are realized by triple-level cells (TLCs), and the blocks supports eight program threshold voltage intervals.

9. The method of claim 8 , wherein the step of using the plurality of program threshold voltage intervals to write the data into one of the blocks comprises:

if the amount of stored data in the flash memory module is less than the first threshold, using only two of the program threshold voltage intervals within the first voltage range to write the data into the one of the blocks; and

if the amount of stored data in the flash memory module is greater than the first threshold, using at least four of the program threshold voltage intervals within the second voltage range to write the data into the one of the blocks.

10. The method of claim 8 , wherein the step of using the plurality of program threshold voltage intervals to write the data into one of the blocks comprises:

if the amount of stored data in the flash memory module is less than the first threshold, using only two of the program threshold voltage intervals within the first voltage range to write the data into the one of the blocks; and

if the amount of stored data in the flash memory module is greater than the first threshold, using eight program threshold voltage intervals within the second voltage range to write the data into the one of the blocks.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2017
From: YANG, TSUNG-CHIEH; KUO, CHUN-CHIEH; LIN, CHING-HUI; SHEN, YANG-CHIH
To: SILICON MOTION INC.
Reel/Frame 042927/0819 →
Priority Claims (1)
TW 100129676 A · Aug 19, 2011 · national
Continuity (5)
Continuation 15235128 · Aug 12, 2016
Continuation 14983566 · Dec 30, 2015
Continuation 14596236 · Jan 14, 2015
Continuation 13491377 · Jun 7, 2012
Related Publication 20170308318A1 · Oct 26, 2017
Cited By (1)
US 12,236,115