IP Library Granted Patent US 12,236,115
Granted Patent B2
US 12,236,115 · App. 18/412,635 · Granted Feb 25, 2025

Flash memory controller

Inventors: Tsung-Chieh Yang (Hsinchu, TW); Chun-Chieh Kuo (Taipei, TW); Ching-Hui Lin (Hsinchu County, TW); Yang-Chih Shen (Taoyuan, TW)
Assignee: Silicon Motion, Inc.
G06F3/0634G06F3/0604G06F3/064G06F3/0679G06F12/0246G11C11/5628G11C11/5642G06F2212/7201G06F2212/7206Y02D10/00
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Quick Facts
Patent No.
US 12,236,115
App. No.
18/412,635
Granted
Feb 25, 2025
Kind
B2
Abstract

A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Claims (12)

1. A method for accessing a flash memory module, wherein the flash memory module comprises a plurality of data blocks, and the method comprises the steps of:

receiving data from a host device;

determining if the data received from the host device is cold data or hot data;

if the data is determined as the cold data, using a two-bit-per-cell mode or a three-bit-per-cell mode to write the data into one of the plurality of data blocks; and

if the data is determined as the hot data, using a one-bit-per-cell mode to write the data into another one of the plurality of data blocks.

2. The method of claim 1 , wherein the plurality of data blocks are realized by triple-level cells (TLCs), and the blocks supports eight plurality of program threshold voltage intervals.

3. The method of claim 1 , wherein the step of determining if the data received from the host device is the cold data or the hot data comprises:

determining if the data received from the host device is the cold data or the hot data according to a file type.

4. The method of claim 1 , wherein the step of determining if the data received from the host device is the cold data or the hot data comprises:

determining if the data received from the host device is the cold data or the hot data according to a file extension.

5. The method of claim 1 , wherein the step of determining if the data received from the host device is the cold data or the hot data comprises:

determining if the data received from the host device is the cold data or the hot data according to a logical address of the data.

Priority Claims (1)
TW 100129676 · Aug 19, 2011 · national
Continuity (11)
Continuation 17324121 · May 19, 2021
Continuation 17030392 · Sep 24, 2020
Continuation 16686200 · Nov 17, 2019
Continuation 16260142 · Jan 29, 2019
Continuation 15985718 · May 22, 2018
Continuation 15643501 · Jul 7, 2017
Continuation 15235128 · Aug 12, 2016
Continuation 14983566 · Dec 30, 2015
Continuation 14596236 · Jan 14, 2015
Continuation 13491377 · Jun 7, 2012
Related Publication 20240152288A1 · May 9, 2024
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