Method of fabricating III-V fin structures and semiconductor device with III-V fin structures

1. A method of fabricating III-V fin structures, comprising:

providing a plurality of fins and a plurality of shallow trench isolations (STIs), wherein each of the fins are sandwiched by two of the STIs;

performing a deposition process to conformally form a group III-V material layer encapsulating an upper portion of each of the fins and covering the STIs;

removing part of the group III-V material layer to expose an end of each of the fins and divide the group III-V material layer into a plurality of U-shaped structures;

removing a first part of each of the fins; and

removing part of each of the U-shaped structures to segment each of the U-shaped structures into two III-V fin structures.

2. The method of fabricating III-V fin structures of claim 1 , further comprising:

after forming the group III-V material layer and before removing the first part of each of the fin, forming a silicon oxide layer to cover the group III-V material layer;

planarizing the silicon oxide layer and the group III-V material layer to remove the part of the group III-V material layer, expose the end of each of the fins and form the U-shaped structures;

shortening two ends of each of the U-shaped structures to form recesses between the silicon oxide layer and each of the fins; and

forming a hard mask filling up the recesses.

3. The method of fabricating III-V fin structures of claim 2 , further comprising:

after forming the III-V fin structures, removing the hard mask.

4. The method of fabricating III-V fin structures of claim 1 , further comprising:

after forming the III-V fin structures, forming an isolating structure between two adjacent III-V fin structures, wherein an upper portion of each of the III-V fin structures protrudes from the isolating structure.

5. The method of fabricating III-V fin structures of claim 1 , wherein the III-V fin structures are disposed on the STIs and do not overlap the fins.

6. The method of fabricating III-V fin structures of claim 1 , wherein after removing the first part of each of the fins, a second part of each of the fins remains, and the second part of each of the fins is lower than the interface between the group III-V material layer and the STIs.

7. The method of fabricating III-V fin structures of claim 1 , wherein the fins comprise silicon.

8. A semiconductor device with III-V fin structures, comprising:

a plurality of fins;

a plurality of shallow trench isolations (STIs), wherein each of the STIs is disposed between the fins;

a plurality of III-V fin structures, wherein each of the STIs has two III-V fin structures disposed thereon; and

a plurality of isolating structures disposed on the fins and STIs, and between the III-V fin structures, wherein an upper portion of each of the III-V fin structures protrudes from the isolating structures.

9. The semiconductor device with III-V fin structures of claim 8 , wherein each of the fins is lower than the interface between the III-V fin structures and the STIs.

10. The semiconductor device with III-V fin structures of claim 8 , further comprising a recess disposed within each of the STIs and filled up by the isolating structures.

11. The semiconductor device with III-V fin structures of claim 8 , wherein the fins comprise silicon.