Reliability caps for high-k dielectric anneals
Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.
1. A method comprising:
depositing a first layer comprised of a metal silicon nitride on a high-k dielectric material;
thermally processing the high-k dielectric material in an oxygen-containing ambient environment with the first layer arranged as a cap between the high-k dielectric material and the oxygen-containing ambient environment; and
after the high-k dielectric material is thermally processed, completely removing the first layer with a wet chemical etching process,
wherein the first layer blocks transport of oxygen from the oxygen-containing ambient environment to the high-k dielectric material.
2. The method of claim 1 wherein the metal silicon nitride is titanium silicon nitride (TiSiN).
3. The method of claim 1 wherein the metal silicon nitride includes a metal selected from the group consisting of titanium (Ti), tantalum (Ta) tungsten (W), niobium (Nb), vanadium (V), zirconium (Zr), hafnium (Hf), chromium (Cr), molybdenum (Mo), and combinations thereof.
4. The method of claim 1 further comprising:
depositing a second layer on the high-k dielectric material,
wherein the second layer is arranged between the first layer and the high-k dielectric material, and the second layer is free of silicon.
5. The method of claim 4 wherein the first layer and the second layer are deposited in the same deposition tool, and the second layer is deposited before the first layer is deposited.
6. The method of claim 4 wherein the first layer and the second layer are deposited in different deposition tools with an air break, and the second layer is deposited before the first layer is deposited.
7. The method of claim 1 wherein the high-k dielectric material is a gate dielectric of a field-effect transistor.
8. The method of claim 1 wherein the first layer is in direct contact with the high-k dielectric material along an interface.
9. The method of claim 8 wherein the first layer is deposited with a graded composition that is depleted of silicon at the interface.
10. The method of claim 1 wherein the first layer is deposited by atomic layer deposition.
11. The method of claim 1 wherein thermally processing the high-k dielectric material comprises:
performing a spike anneal, a soak anneal, and/or a laser spike anneal targeting the high-k dielectric material,
wherein the high-k dielectric material is arranged on a semiconductor layer containing silicon.
12. The method of claim 1 further comprising:
after completely removing the first layer, forming a gate electrode on the high-k dielectric material.
13. The method of claim 1 wherein the first layer has an amorphous structure.
14. The method of claim 1 wherein the metal silicon nitride of the first layer is removed by the wet chemical etching process selective to the high-k dielectric material.
15. The method of claim 8 wherein the metal silicon nitride of the first layer has a concentration of silicon that increases with increasing distance in the first layer from the interface.
16. The method of claim 15 wherein the metal silicon nitride is titanium silicon nitride, and the metal silicon nitride of the first layer has a concentration of titanium that decreases with increasing distance in the first layer from the interface.