IP Library › Granted Patent US 10,186,467
Granted Patent B2
US 10,186,467 · App. 15/649,545 · Granted Jan 22, 2019

Semiconductor package device and method of manufacturing the same

Inventors: Bernd Karl Appelt (Kaohsiung, TW); Kay Stefan Essig (Kaohsiung, TW); Chi-Tsung Chiu (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/3135H01L21/486H01L21/561H01L21/563H01L21/568H01L21/76805H01L21/76879H01L23/3128H01L23/3142H01L23/3157H01L23/367H01L23/481H01L23/49827H01L23/5384H01L23/5389H01L24/19H01L24/20H01L24/27H01L24/32H01L25/0655H01L25/0657H01L23/145H01L23/3677H01L2224/211H01L2224/215H01L2224/32146H01L2225/06524H01L2225/06548H01L2225/06582H01L2924/01022H01L2924/01029
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Quick Facts
Patent No.
US 10,186,467
App. No.
15/649,545
Granted
Jan 22, 2019
Kind
B2
Abstract

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

Claims (40)

1. A semiconductor package device, comprising:

a die having a first surface and a second surface opposite to the first surface, the die comprising a first electrode disposed at the first surface of the die and a second electrode disposed at the second surface of the die;

an adhesive layer disposed on the first surface of the die; and

an encapsulant layer encapsulating the die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

2. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the encapsulant layer, wherein the first conductive layer is in thermal and electrical communication with the second electrode and covers substantially the entire surface of the second electrode.

3. The semiconductor package device of claim 2 , wherein a lateral surface of the encapsulant layer is substantially coplanar with a side surface of the first conductive layer.

4. The semiconductor package device of claim 2 , further comprising a conductive via disposed in the encapsulant layer electrically connected to the first conductive layer.

5. The semiconductor package device of claim 4 , further comprising:

a patterned conductive layer disposed on the encapsulant layer and electrically connected to the conductive via.

6. The semiconductor package device of claim 5 , further comprising a seed layer disposed between the conductive via and the encapsulant layer.

7. The semiconductor package device of claim 1 , further comprising a conductive via disposed in the adhesive layer, wherein at least a portion of a surface of the first electrode is exposed from the adhesive layer and electrically connected to the conductive via.

8. The semiconductor package device of claim 7 , further comprising:

a seed layer disposed between the first electrode and the conductive via and between the conductive via and the adhesive layer.

9. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the second surface of the die.

10. The semiconductor package device of claim 1 , further comprising:

a conductive via disposed in the adhesive layer and electrically connected to the die; and

a patterned conductive layer disposed on the encapsulant layer and electrically connected to the conductive via.

11. The semiconductor package device of claim 2 , further comprising a second conductive layer disposed between the first conductive layer and the second electrode.

12. The semiconductor package device of claim 11 , further comprising a seed layer disposed between the first conductive layer and the second conductive layer.

13. The semiconductor package device of claim 11 , wherein the second conductive layer is in direct contact with the second electrode and covers the second electrode.

14. A method of manufacturing a semiconductor package device, the method comprising:

providing a carrier having a first conductive layer disposed thereon;

attaching a first side of a die to the carrier through an adhesive layer, the die comprising a first electrode disposed at the first side and a second electrode disposed at a second side opposite to the first side;

encapsulating the die and the adhesive layer with an encapsulant such that substantially an entire surface of the second electrode of the die is exposed from the encapsulant; and

removing the carrier.

15. The method of claim 14 , further comprising removing a portion of the first conductive layer and a portion of the adhesive layer to form an opening that exposes the first electrode.

16. The method of claim 15 , further comprising filling the opening with a conductive material to form a first conductive via.

17. The method of claim 14 , further comprising forming a second conductive layer on the encapsulant and electrically connecting the second conductive layer to the second electrode.

18. The method of claim 17 , further comprising:

removing a portion of the first conductive layer and a portion of the adhesive layer to form an opening that exposes the first electrode; and

filling the opening with a conductive material to form a first conductive via,

wherein the formation of the first conductive layer and the first conductive via is performed in a single operation.

19. The method of claim 17 , further comprising:

removing a portion of the first conductive layer and a portion of the adhesive layer to form an opening that exposes the first electrode;

filling the first opening with a conductive material to form a first conductive via; and

forming a second conductive via in the encapsulant.

20. The method of claim 14 , further comprising:

forming a conductive stud adjacent to an area where the die is to be placed on the carrier;

encapsulating the conductive stud when encapsulating the die and the adhesive layer; and

exposing the conductive stud.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2017
From: APPELT, BERND KARL; ESSIG, KAY STEFAN; CHIU, CHI-TSUNG
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 043632/0799 →
Continuity (2)
Provisional Application 62363130 · Jul 15, 2016
Related Publication 20180019221A1 · Jan 18, 2018
Cited By (1)
US 12,419,063