Fabricating method of fin structure with tensile stress and complementary FinFET structure
A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
1. A complementary FinFET structure, comprising:
an N-type FinFET comprising:
a first fin structure;
two shallow trench isolations respectively disposed at two sides of the first fin structure;
two first single diffusion breaks respectively disposed at two ends of the first fin structure, wherein the topmost surface of each of the first single diffusion breaks is not lower than the topmost surface of the first fin structure;
a first gate structure crossing the first fin structure; and
two first source/drain doped regions respectively disposed in the first fin structure at two sides of the first gate structure; and
a P-type FinFET comprising:
a second fin structure;
the shallow trench isolations respectively disposed at two sides of the second fin structure;
two second single diffusion breaks respectively disposed at two ends of the second fin structure, wherein the topmost surface of each of the second single diffusion breaks is lower than the topmost surface of the second fin structure, the topmost surface of each of the second single diffusion breaks is aligned with the topmost surface of each of the shallow trench isolations, and a bottommost surface of each of the first single diffusion breaks, a bottommost surface of each of the second single diffusion breaks, a bottommost surface of each of the shallow trench isolations are aligned;
a second gate structure crossing the second fin structure; and
two second source/drain doped regions respectively disposed in the second fin structure at two sides of the second gate structure.
2. The complementary FinFET structure of claim 1 , wherein the topmost surface of each of the first single diffusion breaks is higher than the topmost surface of the first fin structure.
3. The complementary FinFET structure of claim 1 , wherein the topmost surface of each of the first single diffusion breaks is aligned with the topmost surface of the first fin structure.
4. The complementary FinFET structure of claim 1 , wherein the topmost surface of each of the first single diffusion breaks is higher than the topmost surface of each of the shallow trench isolations.
5. The complementary FinFET structure of claim 1 , wherein the topmost surface of the first fin structure is aligned with the topmost surface of the second fin structure.