Apparatuses and methods for accessing hybrid memory system
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a memory array including a plurality of memory cells; a memory controller that transmits a command signal, address signals and further provides and receives data signals; a first port including: a first command terminal that receives the first command signal from the memory controller; first address terminals that receive first address signals from the memory controller; and first data terminals that receive first data signals from the memory controller and further transmit first data signals to the memory controller; and a second port including: a second command terminal that receives a second command signal from the memory controller; second address terminals that receive second address signals from the memory controller; and second data terminals that receive second data signals from an external apparatus other than the memory controller and further transmit second data signals to the external apparatus.
1. An apparatus comprising:
a first memory including first and second ports, each port associated with a respective channel;
a second memory including third and fourth ports, each port associated with a respective channel; and
a controller configured to control each of the first and second memories to perform a data read operation and a data write operation;
wherein the first port includes a first set of data terminals coupled to the controller and is configured to transfer second data between the first memory and the controller, and the second port includes a second set of data terminals,
wherein the third port includes a third set of data terminals coupled to the controller and is configured to transfer third data between the second memory and the controller, and the fourth port includes a fourth set of data terminals coupled to the second set of data terminals of the second port of the first memory, and
wherein the first and second memories are configured to transfer first data therebetween through the second and fourth ports without the first data being temporarily fetched in the controller.
2. The apparatus of claim 1 , wherein the first memory includes a plurality of volatile memory cells and wherein the second memory includes a plurality of non-volatile memory cells.
3. The apparatus of claim 1 , wherein the controller is further configured to provide a first command to the second port, the first command being indicative of a data read operation to cause the second port to provide the first data, and
wherein the controller is further configured to provide a second command to the fourth port, the second command being indicative of a data write operation to cause the fourth port to receive the first data.
4. The apparatus of claim 1 , wherein the controller is further configured to provide a first command indicative of the data read operation to the first memory and further configured to provide a second command indicative of the data write operation to the second memory,
wherein the first memory is configured to provide the first data responsive to the first command, and
wherein the second memory is configured to store the first data responsive to the second command.
5. The apparatus of claim 4 , further comprising:
a data bus interconnecting the controller and the first and second memories with one another,
wherein the first memory is further configured to transfer second data between the first memory and the controller,
wherein the second memory is further configured to transfer third data between the second memory and the controller, and
wherein each of the first, second and third data is transferred through the data bus.
6. The apparatus of claim 5 , further comprising:
a first chip select signal line from the controller and the first memory; and
a second chip select signal line from the controller and the second memory,
wherein the controller is configured to provide the first command while activating the first chip select signal line, and further configured to provide the second command while activating the second chip select signal line.
7. The apparatus of claim 5 , wherein the controller is further configured to provide address signals indicative of a first memory cell in the first memory while transmitting the first command, and
wherein the controller is further configured to provide the address signals indicative of a second memory cell in the second memory while transmitting the second command.
8. The apparatus of claim 5 , wherein the first command includes a first chip identifier indicative of the first memory and wherein the second command includes a second chip identifier indicative of the second memory.