Field effect transistor having an air-gap gate sidewall spacer and method
A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.
1. A method comprising:
forming a transistor comprising:
source/drain regions;
at least one channel region between the source/drain regions;
a gate adjacent to the channel region and having a gate cap and a sacrificial gate sidewall spacer; and
metal plugs on the source/drain regions, the sacrificial gate sidewall spacer being between the metal plugs and the gate and the metal plugs having plug caps;
selectively etching the sacrificial gate sidewall spacer to create a cavity that exposes sidewalls of the gate and the gate cap;
forming an air-gap gate sidewall spacer in the cavity by depositing a dielectric spacer layer such that an air-gap is formed in a first portion of the cavity adjacent to the gate and contained entirely below a level of a top of the gate and such that the dielectric spacer layer fills a second portion of the cavity adjacent to the gate cap and covers the air-gap;
removing the dielectric spacer layer from above the plug caps and the gate cap;
depositing interlayer dielectric material over the plug caps, the air-gap gate sidewall spacer and the gate cap; and
forming a gate contact comprising:
forming a gate contact opening that is aligned above the gate and that extends through the interlayer dielectric material to top surfaces of the gate cap and the air-gap gate sidewall spacer;
extending the gate contact opening through the gate cap to the gate; and
filling the gate contact opening with a conductor to form the gate contact.
2. The method of claim 1 , the gate comprising a replacement metal gate.
3. The method of claim 1 , the sacrificial gate sidewall spacer, the gate cap and the plug caps comprising different dielectric materials.
4. The method of claim 1 , the gate cap, the plug caps and the dielectric spacer layer comprising different dielectric materials.
5. The method of claim 1 , the gate contact opening being formed so as to land on a portion of the gate adjacent to an active region of the transistor.
6. The method of claim 1 , the air-gap gate sidewall spacer being formed on a remaining portion of the sacrificial gate sidewall spacer.
7. A method comprising:
forming a transistor comprising:
source/drain regions;
at least one channel region between the source/drain regions;
a gate adjacent to the channel region and having a gate cap and a sacrificial gate sidewall spacer; and
metal plugs on the source/drain regions, the sacrificial gate sidewall spacer being between the metal plugs and the gate and the metal plugs having plug caps;
selectively etching the sacrificial gate sidewall spacer to create a cavity that exposes sidewalls of the gate and the gate cap; and
etching back exposed sidewalls of the gate cap such that a first portion of the cavity adjacent to the gate has a first width and such that a second portion of the cavity adjacent to the gate cap has a second width that is greater than the first width; and
forming an air-gap gate sidewall spacer in the cavity by depositing a dielectric spacer layer such that an air-gap is formed in the first portion of the cavity and such that the dielectric spacer layer fills the second portion.
8. The method of claim 7 , the gate comprising a replacement metal gate.
9. The method of claim 7 , the sacrificial gate sidewall spacer, the gate cap and the plug caps comprising different materials.
10. The method of claim 7 , the gate cap, the plug caps and the dielectric spacer layer comprising different materials.
11. The method of claim 7 , further comprising:
removing the dielectric spacer layer from above the plug caps and the gate cap; depositing interlayer dielectric material over the plug caps, the air-gap gate sidewall spacer and the gate cap; and
forming a gate contact comprising:
forming a gate contact opening that is aligned above the gate and that extends through the interlayer dielectric material to top surfaces of the gate cap and the air-gap gate sidewall spacer;
extending the gate contact opening through the gate cap to the gate; and
filling the gate contact opening with a conductor to form the gate contact.
12. The method of claim 11 , the gate contact opening being formed so as to land on the gate adjacent to an active region of the transistor.
13. The method of claim 7 , the air-gap gate sidewall spacer being formed on a remaining portion of the sacrificial gate sidewall spacer.