METHOD OF INCREASING EMBEDDED 3D METAL-INSULATOR-METAL (MIM) CAPACITOR CAPACITANCE DENSITY FOR WAFER LEVEL PACKAGING
Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plurality of polymer layers to form at least one via that extends from a top surface of an uppermost polymer layer to a top surface of the metal layer; and forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the at least one via and over a portion of the metal layer and the plurality of polymer layers.
1 . A method of processing a substrate, comprising:
providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer;
depositing a plurality of polymer layers atop the substrate;
patterning the plurality of polymer layers to form at least one via that extends from a top surface of an uppermost polymer layer to a top surface of the metal layer; and
forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the at least one via and over a portion of the metal layer and the plurality of polymer layers.
2 . The method of claim 1 , further comprising:
forming at least one of the at least one via with an aspect ratio of approximately 2:1 or greater.
3 . The method of claim 1 , further comprising:
forming a first electrical connection with the top surface of the metal layer on a top surface of an uppermost polymer layer; and
forming a second electrical connection with a top surface of the 3D MIM capacitance stack.
4 . The method of claim 3 , wherein the first electrical connection and the second electrical connection are copper or aluminum.
5 . The method of claim 1 , further comprising:
patterning the plurality of polymer layers by forming a photoresist layer on the uppermost polymer layer and using a dry etch process to create the at least one via.
6 . The method of claim 1 , wherein the metal layer is copper or aluminum.
7 . The method of claim 1 , wherein the polymer dielectric layer is polyimide, polybenzoxazole, or benzocyclobutene (BCB).
8 . The method of claim 1 , wherein at least one of the plurality of polymer layers is a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
9 . A method of processing a substrate, comprising:
providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer;
depositing a first polymer layer atop the substrate;
patterning the first polymer layer to form a first opening to a top surface of the metal layer;
curing the first polymer layer;
forming a first contact within the first opening to the top surface of the metal layer;
forming a first metal pad over the first contact;
depositing a second polymer layer atop the substrate;
patterning the second polymer layer to form a second opening to the top surface of the first metal pad;
curing the second polymer layer;
forming a second contact within the second opening to a top surface of the first metal pad;
forming a second metal pad over the second contact;
depositing a third polymer layer atop the substrate;
patterning the third polymer layer to form a third opening to the top surface of the second metal pad;
curing the third polymer layer;
patterning the first, second, and third polymers layer to form a plurality of vias to the top surface of the metal layer; and
forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the plurality of vias and over a portion of the metal layer, the first polymer layer, the second polymer layer, and the third polymer layer.
10 . The method of claim 9 , further comprising:
patterning the first, second, and third polymer layers by forming a photoresist layer on the third polymer layer and using a dry etch process to create the plurality of vias.
11 . The method of claim 9 , wherein the substrate is silicon, glass, ceramic, dielectric, or epoxy mold compound.
12 . The method of claim 9 , wherein the first metal pad and the second metal pad are copper or aluminum.
13 . The method of claim 9 , wherein the metal layer is copper or aluminum.
14 . The method of claim 9 , wherein the polymer dielectric layer is polyimide, polybenzoxazole, or benzocyclobutene (BCB).
15 . The method of claim 9 , wherein the first polymer layer, the second polymer layer, or the third polymer layer is a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
16 . A semiconductor device, comprising:
at least two polymer layers over a metal layer on a substrate; and
a three-dimensional metal-insulator-metal (3D MIM) capacitance stack formed in at least one via, wherein the at least one via extends from a top surface of an uppermost polymer layer to the metal layer, wherein an aspect ratio of at least one of the at least one via is approximately 2:1 or greater.
17 . The semiconductor device of claim 16 , further comprising:
a first metal pad on the uppermost polymer layer that is in electrical contact with the metal layer; and
a second metal pad on that is in electrical contact with a top surface of the 3D MIM capacitance stack.
18 . The semiconductor device of claim 17 , wherein the first metal pad and the second metal pad are copper or aluminum.
19 . The semiconductor device of claim 16 , wherein at least one of the at least two polymer layers is a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
20 . The semiconductor device of claim 16 , wherein the substrate is silicon, glass, ceramic, dielectric or epoxy mold compound.