Hardware trace and introspection for productivity platform using a system-on-chip
An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.
1. An integrated circuit, comprising:
programmable circuitry configured to implement an overlay circuit specified by an overlay, wherein the overlay circuit includes a trace buffer configured to receive a probed signal from circuitry within the overlay circuit;
wherein the trace buffer is configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory;
a processor coupled to the programmable circuitry and configured to control operation of the trace buffer, wherein the processor is configured to read the trace data from the runtime allocated memory; and
wherein the processor is configured to execute a software library for a high-productivity language for controlling capture of trace data from the circuitry within the overlay circuit and for analyzing the trace data from the runtime allocated memory.
2. The integrated circuit of claim 1 , wherein the trace buffer comprises:
a direct memory access circuit configured to write the trace data to the runtime allocated memory.
3. The integrated circuit of claim 2 , wherein the trace buffer comprises:
a first-in-first-out memory coupled to the direct memory access circuit, wherein the first-in-first out memory is configured to store the trace data, wherein the direct memory access circuit reads the trace data from the first-in-first-out memory for writing to the runtime allocated memory.
4. The integrated circuit of claim 3 , wherein the trace buffer comprises:
a trigger circuit configured to store data within the first-in-first-out memory.
5. The integrated circuit of claim 1 , wherein the trace buffer further comprises:
a switch coupled to a plurality of signals, wherein the switch is controllable by the processor to pass a selected signal of the plurality of signals as the probed signal.
6. The integrated circuit of claim 1 , wherein the processor, executing the software library, is configured to arm the trace buffer.
7. The integrated circuit of claim 1 , wherein the processor, executing the software library, is configured to control the trace buffer.
8. The integrated circuit of claim 1 , wherein the processor is configured to provide trace data to a data processing system via a browser-enabled interface.
9. The integrated circuit of claim 1 , wherein the processor is configured to generate a visualization of the trace data that is provided to a data processing system via a browser-enabled interface.
10. The integrated circuit of claim 1 , wherein the processor is configured to modify an application implemented within the programmable circuitry in response to detecting a condition in the trace data.
11. A method, comprising:
providing, within an integrated circuit, a programmable circuitry configured to implement an overlay circuit specified by an overlay, wherein the overlay circuit includes a trace buffer configured to receive a probed signal from circuitry within the overlay circuit;
wherein the trace buffer is configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory;
providing, within the integrated circuit, a processor coupled to the programmable circuitry and configured to control operation of the trace buffer, wherein the processor is configured to read the trace data from the runtime allocated memory; and
wherein the processor is configured to execute a software library for a high-productivity language for controlling capture of trace data from the circuitry within the overlay circuit and for analyzing the trace data from the runtime allocated memory.
12. The method of claim 11 , further comprising:
providing a direct memory access circuit within the trace buffer configured to write the trace data to the runtime allocated memory.
13. The method of claim 12 , further comprising:
providing a first-in-first-out memory within the trace buffer, wherein the first-in-first out memory is coupled to the direct memory access circuit and is configured to store the trace data, wherein the direct memory access circuit reads the trace data from the first-in-first-out memory for writing to the runtime allocated memory.
14. The method of claim 13 , further comprising:
providing a trigger circuit within the trace buffer, wherein the trigger circuit is configured to store data within the first-in-first-out memory.
15. The method of claim 11 , further comprising:
providing a switch coupled to a plurality of signals, wherein the switch is controllable by the processor to pass a selected signal of the plurality of signals as the probed signal.
16. The method of claim 11 , wherein the processor, executing the software library, is configured to arm the trace buffer.
17. The method of claim 11 , wherein the processor, executing the software library, is configured to control the trace buffer.
18. The method of claim 11 , wherein the processor is configured to generate a visualization of the trace data that is provided to a data processing system via a browser-enabled interface.
19. An integrated circuit, comprising:
programmable circuitry configured to implement an overlay circuit specified by an overlay, wherein the overlay circuit includes a trace buffer configured to receive a probed signal from circuitry within the overlay circuit;
wherein the trace buffer is configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory;
a processor coupled to the programmable circuitry and configured to control operation of the trace buffer, wherein the processor is configured to read the trace data from the runtime allocated memory; and
wherein the trace buffer comprises a direct memory access circuit configured to write the trace data to the runtime allocated memory.
20. The integrated circuit of claim 19 , wherein the processor is configured to execute a software library for a high-productivity language for controlling capture of trace data from the circuitry within the overlay circuit and for analyzing the trace data from the runtime allocated memory.